Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology. - Heechun Park; Kyungjoon Chang; Jooyeon Jeong; Jaehoon Ahn; Ki-Seok Chung; Taewhan Kim 001 (ISOCC, 2021)

Utilizing Middle-of-Line Resource in Filler Cells for Fixing Routing Failures. - Jooyeon Jeong; Taewhan Kim 001 (MWSCAS, 2021)

Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement. - Eunsol Jeong; Heechun Park; Jooyeon Jeong; Taewhan Kim 001 (MWSCAS, 2021)

Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis. - Sehyeon Chung; Jooyeon Jeong; Taewhan Kim 001 (ISLPED, 2022)

Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility. - Jooyeon Jeong; Sehyeon Chung; Kyeongrok Jo; Taewhan Kim 001 (DATE, 2023)

Binding Multi-bit Flip-flop Cells through Design and Technology Co-optimization. - Jooyeon Jeong; Taewhan Kim 001 (DAC, 2024)

Placement legalization for heterogeneous cells of non-integer multiple-heights. - Jooyeon Jeong; Taewhan Kim 001 (Integr., 2024)