A mechanism for reducing the cost of branches in RISC architectures. - Antonio González 001; José María Llabería; Jordi Cortadella (Microprocess. Microprogramming, 1988)

Designing a branch target buffer for executing branches with zero time cost in a RISC processor. - Jordi Cortadella; Teodor Jové (Microprocess. Microprogramming, 1988)

Dynamic RAM for on-chip instruction caches. - Jordi Cortadella; Teodor Jové (SIGARCH Comput. Archit. News, 1988)

Reduced instruction buffer for RISC architectures. - Teodor Jové; Jordi Cortadella (Microprocessing and Microprogramming, 1989)

Scheduling in a continuous area-time design space. - Jordi Cortadella; Rosa M. Badia; Eduard Ayguadé (Microprocessing and Microprogramming, 1991)

Evaluation of A + B = K Conditions Without Carry Propagation. - Jordi Cortadella; José M. Llabería (IEEE Trans. Computers, 1992)

Comments on 'Using cache mechanisms to exploit nonrefreshing DRAM's for on-chip memories'. - Jordi Cortadella; Teodor Jové (IEEE J. Solid State Circuits, 1992)

Division with speculation of quotient digits. - Jordi Cortadella; Tomás Lang (IEEE Symposium on Computer Arithmetic, 1993)

Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphs. - Enric Pastor; Jordi Cortadella (ICCAD, 1993)

An Efficient Unique State Coding Algorithm for Signal Transition Graphs. - Enric Pastor; Jordi Cortadella (ICCD, 1993)

Glass: a graph-theoretical approach for global binding. - Rosa M. Badia; Jordi Cortadella (Microprocess. Microprogramming, 1993)

Session B2: Processor Architecture II. - Jordi Cortadella (Microprocess. Microprogramming, 1993)

Resource-constrained pipelining based on loop transformations. - Fermín Sánchez; Jordi Cortadella (Microprocess. Microprogramming, 1993)

Chairmen's introduction. - Mateo Valero; Jordi Cortadella; Antonio González 001 (Microprocess. Microprogramming, 1993)

Petri Net Analysis Using Boolean Manipulation. - Enric Pastor; Oriol Roig; Jordi Cortadella; Rosa M. Badia (Application and Theory of Petri Nets, 1994)

Designing asynchronous circuits from behavioural specifications with internal conflicts. - Jordi Cortadella; Luciano Lavagno; Peter Vanbekbergen; Alex Yakovlev (ASYNC, 1994)

Design and Prototyping of Digital Signal Processing (DSP) Systems: Introduction. - Jordi Cortadella; José A. B. Fortes; Edward A. Lee (HICSS (1), 1994)

High-Radix Division and Square-Root with Speculation. - Jordi Cortadella; Tomás Lang (IEEE Trans. Computers, 1994)

Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets. - Oriol Roig; Jordi Cortadella; Enric Pastor (Application and Theory of Petri Nets, 1995)

Hierarchical gate-level verification of speed-independent circuits. - Oriol Roig; Jordi Cortadella; Enric Pastor (ASYNC, 1995)

Checking signal transition graph implementability by symbolic BDD traversal. - Alex Kondratyev; Jordi Cortadella; Michael Kishinevsky; Enric Pastor; Oriol Roig; Alexandre Yakovlev (ED&TC, 1995)

A new look at the conditions for the synthesis of speed-independent circuits. - Enric Pastor; Jordi Cortadella; Oriol Roig (Great Lakes Symposium on VLSI, 1995)

Synthesizing Petri nets from state-based models. - Jordi Cortadella; Michael Kishinevsky; Luciano Lavagno; Alexandre Yakovlev (ICCAD, 1995)

High-level synthesis techniques for reducing the activity of functional units. - Enric Musoll; Jordi Cortadella (ISLPD, 1995)

Scheduling and resource binding for low power. - Enric Musoll; Jordi Cortadella (ISSS, 1995)

Complete state encoding based on the theory of regions. - Jordi Cortadella; Michael Kishinevsky; Alex Kondratyev; Luciano Lavagno; Alex Yakovlev (ASYNC, 1996)

Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits. - Marco A. Peña; Jordi Cortadella (ASYNC, 1996)

Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis. - Jordi Cortadella; Michael Kishinevsky; Alex Kondratyev; Luciano Lavagno; Alexandre Yakovlev (DAC, 1996)

Optimizing CMOS Circuits for Low Power Using Transistor Reordering. - Enric Musoll; Jordi Cortadella (ED&TC, 1996)

RESIS: A New Methodology for Register Optimization in Software Pipelining. - Fermín Sánchez; Jordi Cortadella (Euro-Par, Vol. II, 1996)

Coupling Asynchrony and Interrupts: Place Chart Nets. - Michael Kishinevsky; Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Alexander Taubin; Alexandre Yakovlev (ICATPN, 1997)

Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis. - Alex Kondratyev; Michael Kishinevsky; Jordi Cortadella; Luciano Lavagno; Alexandre Yakovlev (ASYNC, 1997)

Partial order based approach to synthesis of speed-independent circuits. - Alexei L. Semenov; Alexandre Yakovlev; Enric Pastor; Marco A. Peña; Jordi Cortadella; Luciano Lavagno (ASYNC, 1997)

Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits. - Oriol Roig; Jordi Cortadella; Marco A. Peña; Enric Pastor (DAC, 1997)

Synthesis of Speed-Independent Circuits from STG-Unfolding Segment. - Alexei L. Semenov; Alexandre Yakovlev; Enric Pastor; Marco A. Peña; Jordi Cortadella (DAC, 1997)

Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis. - Jordi Cortadella; Michael Kishinevsky; Alex Kondratyev; Luciano Lavagno; Alexandre Yakovlev (ED&TC, 1997)

Exploiting the locality of memory references to reduce the address bus energy. - Enric Musoll; Tomás Lang; Jordi Cortadella (ISLPED, 1997)

A region-based theory for state assignment in speed-independent circuits. - Jordi Cortadella; Michael Kishinevsky; Alex Kondratyev; Luciano Lavagno; Alexandre Yakovlev (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Combining Structural and Symbolic Methods for the Verification of Concurrent Systems. - Jordi Cortadella (ACSD, 1998)

Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings. - Alex Kondratyev; Jordi Cortadella; Michael Kishinevsky; Luciano Lavagno; Alexander Taubin; Alexandre Yakovlev (ACSD, 1998)

Asynchronous Interface Specification, Analysis and Synthesis. - Michael Kishinevsky; Jordi Cortadella; Alex Kondratyev (DAC, 1998)

Efficient Encoding Schemes for Symbolic Analysis of Petri Nets. - Enric Pastor; Jordi Cortadella (DATE, 1998)

Lazy transition systems: application to timing optimization of asynchronous circuits. - Jordi Cortadella; Michael Kishinevsky; Alex Kondratyev; Luciano Lavagno; Alexander Taubin; Alexandre Yakovlev (ICCAD, 1998)

Extension of the working-zone-encoding method to reduce the energy on the microprocessor data bus. - Tomás Lang; Enric Musoll; Jordi Cortadella (ICCD, 1998)

Register-Transfer Level Transformations for Low-Power Data-Paths. - Enric Musoll; Jordi Cortadella (Integr. Comput. Aided Eng., 1998)

The Use of Petri Nets for the Design and Verification of Asynchronous Circuits and Systems. - Alex Kondratyev; Michael Kishinevsky; Alexander Taubin; Jordi Cortadella; Luciano Lavagno (J. Circuits Syst. Comput., 1998)

Reducing Register Pressure in Software Pipelining. - Fermín Sánchez; Jordi Cortadella (J. Inf. Sci. Eng., 1998)

Deriving Petri Nets for Finite Transition Systems. - Jordi Cortadella; Michael Kishinevsky; Luciano Lavagno; Alexandre Yakovlev (IEEE Trans. Computers, 1998)

Structural methods for the synthesis of speed-independent circuits. - Enric Pastor; Jordi Cortadella; Alex Kondratyev; Oriol Roig (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Working-zone encoding for reducing the energy in microprocessor address buses. - Enric Musoll; Tomás Lang; Jordi Cortadella (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Structural Methods to Improve the Symbolic Analysis of Petri Nets. - Enric Pastor; Jordi Cortadella; Marco A. Peña (ICATPN, 1999)

Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications. - Alexander Taubin; Alex Kondratyev; Jordi Cortadella; Luciano Lavagno (ASYNC, 1999)

Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems. - Alex Kondratyev; Jordi Cortadella; Michael Kishinevsky; Luciano Lavagno; Alexandre Yakovlev (DAC, 1999)

CAD Directions for High Performance Asynchronous Circuits. - Ken S. Stevens; Shai Rotem; Steven M. Burns; Jordi Cortadella; Ran Ginosar; Michael Kishinevsky; Marly Roncken (DAC, 1999)

A Radix-16 SRT Division Unit with Speculation of the Quotient Digits. - Gianluca Cornetta; Jordi Cortadella (Great Lakes Symposium on VLSI, 1999)

Synthesis of asynchronous control circuits with automatically generated relative timing assumptions. - Jordi Cortadella; Michael Kishinevsky; Steven M. Burns; Ken S. Stevens (ICCAD, 1999)

What is the cost of delay insensitivity? - Hiroshi Saito; Alex Kondratyev; Jordi Cortadella; Luciano Lavagno; Alexandre Yakovlev (ICCAD, 1999)

Optimal exploration of the unrolling degree for software pipelining. - Fermín Sánchez; Jordi Cortadella; Rosa M. Badia (J. Syst. Archit., 1999)

Logic decomposition of speed-independent circuits. - Alex Kondratyev; Jordi Cortadella; Michael Kishinevsky; Luciano Lavagno; Alexandre Yakovlev (Proc. IEEE, 1999)

Decomposition and technology mapping of speed-independent circuits using Boolean relations. - Jordi Cortadella; Michael Kishinevsky; Alex Kondratyev; Luciano Lavagno; Enric Pastor; Alexandre Yakovlev (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

A Relational View of Subgraph Isomorphism. - Jordi Cortadella; Gabriel Valiente (RelMiCS, 2000)

Hardware and Petri Nets: Application to Asynchronous Circuit Design. - Jordi Cortadella; Michael Kishinevsky; Alex Kondratyev; Luciano Lavagno; Alexandre Yakovlev (ICATPN, 2000)

Formal Verification of Safety Properties in Timed Circuits. - Marco A. Peña; Jordi Cortadella; Enric Pastor; Alex Kondratyev (ASYNC, 2000)

Task generation and compile-time scheduling for mixed data-control embedded software. - Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Marc Massot; Sandra Moral; Claudio Passerone; Yosinori Watanabe; Alberto L. Sangiovanni-Vincentelli (DAC, 2000)

A Multi-Radix Approach to Asynchronous Division. - Gianluca Cornetta; Jordi Cortadella (ASYNC, 2001)

Asynchronous multipliers with variable-delay counters. - Gianluca Cornetta; Jordi Cortadella (ICECS, 2001)

Symbolic Analysis of Bounded Petri Nets. - Enric Pastor; Jordi Cortadella; Oriol Roig (IEEE Trans. Computers, 2001)

Synthesis of Reactive Systems: Application to Asynchronous Circuit Design. - Josep Carmona 001; Jordi Cortadella; Enric Pastor (Concurrency and Hardware Design, 2002)

Quasi-Static Scheduling of Independent Tasksfor Reactive Systems. - Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Claudio Passerone; Yosinori Watanabe (ICATPN, 2002)

A Case Study for the Verification of Complex Timed Circuits: IPCMOS. - Marco A. Peña; Jordi Cortadella; Alexander B. Smirnov; Enric Pastor (DATE, 2002)

Input/Output Compatibility of Reactive Systems. - Josep Carmona 001; Jordi Cortadella (FMCAD, 2002)

Bi-Decomposition and Tree-Height Reduction for Timing Optimization. - Jordi Cortadella (IWLS, 2002)

Logic Design of Asynchronous Circuits (Tutorial Abstract). - Jordi Cortadella; Alexandre Yakovlev; Jim D. Garside (ASP-DAC/VLSI Design, 2002)

A structural encoding technique for the synthesis of asynchronous circuits. - Josep Carmona 001; Jordi Cortadella; Enric Pastor (Fundam. Informaticae, 2002)

Design of Asynchronous Controllers with Delay Insensitive Interface. - Hiroshi Saito; Alex Kondratyev; Jordi Cortadella; Luciano Lavagno; Alex Yakovlev; Takashi Nanya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions. - Jordi Cortadella; Michael Kishinevsky; Steven M. Burns; Alex Kondratyev; Luciano Lavagno; Ken S. Stevens; Alexander Taubin; Alexandre Yakovlev (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Synthesis of Asynchronous Hardware from Petri Nets. - Josep Carmona 001; Jordi Cortadella; Victor Khomenko; Alexandre Yakovlev (Lectures on Concurrency and Petri Nets, 2003)

Quasi-Static Scheduling for Concurrent Architectures. - Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Yosinori Watanabe (ACSD, 2003)

ILP Models for the Synthesis of Asynchronous Control Circuits. - Josep Carmona 001; Jordi Cortadella (ICCAD, 2003)

Timing-driven logic bi-decomposition. - Jordi Cortadella (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Verification of timed circuits with symbolic delays. - Robert Clarisó; Jordi Cortadella (ASP-DAC, 2004)

Handshake Protocols for De-Synchronization. - Ivan Blunno; Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Kelvin Lwin; Christos P. Sotiriou (ASYNC, 2004)

From Synchronous to Asynchronous: An Automatic Approach. - Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Kelvin Lwin; Christos P. Sotiriou (DATE, 2004)

Coping with The Variability of Combinational Logic Delays. - Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Christos P. Sotiriou (ICCD, 2004)

Bridging the Gap between Asynchronous Design and Designers. - Peter A. Beerel; Jordi Cortadella; Alex Kondratyev (VLSI Design, 2004)

Boolean Decomposition Using Two-literal Divisors. - Nilesh Modi; Jordi Cortadella (VLSI Design, 2004)

Quasi-static Scheduling for Concurrent Architectures. - Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Alexander Taubin; Yosinori Watanabe (Fundam. Informaticae, 2004)

Derivation of Non-structural Invariants of Petri Nets Using Abstract Interpretation. - Robert Clarisó; Enric Rodríguez-Carbonell; Jordi Cortadella (ICATPN, 2005)

Quasi-static scheduling of independent tasks for reactive systems. - Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Claudio Passerone; Yosinori Watanabe (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Synchronous Elastic Circuits. - Michael Kishinevsky; Jordi Cortadella; Bill Grundmann; Sava Krstic; John O'Leary (CSR, 2006)

State encoding of large asynchronous controllers. - Josep Carmona 001; Jordi Cortadella (DAC, 2006)

Synthesis of synchronous elastic architectures. - Jordi Cortadella; Michael Kishinevsky; Bill Grundmann (DAC, 2006)

Synchronous Elastic Networks. - Sava Krstic; Jordi Cortadella; Michael Kishinevsky; John O'Leary (FMCAD, 2006)

Dominator-based partitioning for delay optimization. - David Bañeres; Jordi Cortadella; Michael Kishinevsky (ACM Great Lakes Symposium on VLSI, 2006)

From molecular interactions to gates: a systematic approach. - Josep Carmona 001; Jordi Cortadella; Yousuke Takada; Ferdinand Peper (ICCAD, 2006)

Performance analysis of concurrent systems with early evaluation. - Jorge Júlvez; Jordi Cortadella; Michael Kishinevsky (ICCAD, 2006)

Synthesis of asynchronous controllers using integer linear programming. - Josep Carmona 001; José Manuel Colom; Jordi Cortadella; Fernando García-Vallés (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications. - Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Christos P. Sotiriou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

A Compositional Method for the Synthesis of Asynchronous Communication Mechanisms. - Kyller Costa Gorgônio; Jordi Cortadella; Fei Xia 001 (ICATPN, 2007)

Synchronous Elastic Circuits with Early Evaluation and Token Counterflow. - Jordi Cortadella; Michael Kishinevsky (DAC, 2007)

Layout-aware gate duplication and buffer insertion. - David Bañeres; Jordi Cortadella; Michael Kishinevsky (DATE, 2007)

A general model for performance optimization of sequential systems. - Dmitry Bufistov; Jordi Cortadella; Michael Kishinevsky; Sachin S. Sapatnekar (ICCAD, 2007)

Design Automation of Real-Life Asynchronous Devices and Systems. - Alexander Taubin; Jordi Cortadella; Luciano Lavagno; Alex Kondratyev; Ad M. G. Peeters (Found. Trends Electron. Des. Autom., 2007)

Verification of Concurrent Systems with Parametric Delays Using Octahedra. - Robert Clarisó; Jordi Cortadella (Fundam. Informaticae, 2007)

Automating Synthesis of Asynchronous Communication Mechanisms. - Kyller Costa Gorgônio; Jordi Cortadella; Fei Xia 001; Alexandre Yakovlev (Fundam. Informaticae, 2007)

The octahedron abstract domain. - Robert Clarisó; Jordi Cortadella (Sci. Comput. Program., 2007)

Time elastic digital systems and Petri Nets. - Michael Kishinevsky; Jordi Cortadella (ACSD, 2008)

A Symbolic Algorithm for the Synthesis of Bounded Petri Nets. - Josep Carmona 001; Jordi Cortadella; Michael Kishinevsky; Alex Kondratyev; Luciano Lavagno; Alexandre Yakovlev (Petri Nets, 2008)

A Region-Based Algorithm for Discovering Petri Nets from Event Logs. - Josep Carmona 001; Jordi Cortadella; Michael Kishinevsky (BPM, 2008)

Performance optimization of elastic systems using buffer resizing and buffer insertion. - Dmitry Bufistov; Jorge Júlvez; Jordi Cortadella (ICCAD, 2008)

Correct-by-construction microarchitectural pipelining. - Timothy Kam; Michael Kishinevsky; Jordi Cortadella; Marc Galceran Oms (ICCAD, 2008)

Hardware Synthesis for Asynchronous Communications Mechanisms. - Kyller Costa Gorgônio; Jordi Cortadella (SCCC, 2008)

Formal methods for the analysis and synthesis of nanometer-scale cellular arrays. - Josep Carmona 001; Jordi Cortadella; Yousuke Takada; Ferdinand Peper (ACM J. Emerg. Technol. Comput. Syst., 2008)

Encoding Large Asynchronous Controllers With ILP Techniques. - Josep Carmona 001; Jordi Cortadella (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Elasticity and Petri Nets. - Jordi Cortadella; Michael Kishinevsky; Dmitry Bufistov; Josep Carmona 001; Jorge Júlvez (Trans. Petri Nets Other Model. Concurr., 2008)

Genet: A Tool for the Synthesis and Mining of Petri Nets. - Josep Carmona 001; Jordi Cortadella; Michael Kishinevsky (ACSD, 2009)

Scheduling Synchronous Elastic Designs. - Josep Carmona 001; Jorge Júlvez; Jordi Cortadella; Michael Kishinevsky (ACSD, 2009)

Divide-and-Conquer Strategies for Process Mining. - Josep Carmona 001; Jordi Cortadella; Michael Kishinevsky (BPM, 2009)

Retiming and recycling for elastic systems with early evaluation. - Dmitry Bufistov; Jordi Cortadella; Marc Galceran Oms; Jorge Júlvez; Michael Kishinevsky (DAC, 2009)

Speculation in elastic systems. - Marc Galceran Oms; Jordi Cortadella; Michael Kishinevsky (DAC, 2009)

Enabling adaptability through elastic clocks. - Emre Tuncer; Jordi Cortadella; Luciano Lavagno (DAC, 2009)

Variable-latency design by function speculation. - David Bañeres; Jordi Cortadella; Michael Kishinevsky (DATE, 2009)

Timing-driven N-way decomposition. - David Bañeres; Jordi Cortadella; Michael Kishinevsky (ACM Great Lakes Symposium on VLSI, 2009)

Multi-level clustering for clock skew optimization. - Jonas Casanova; Jordi Cortadella (ICCAD, 2009)

A performance analytical model for Network-on-Chip with constant service time routers. - Nikita Nikitin; Jordi Cortadella (ICCAD, 2009)

A Recursive Paradigm to Solve Boolean Relations. - David Bañeres; Jordi Cortadella; Michael Kishinevsky (IEEE Trans. Computers, 2009)

Elastic Circuits. - Josep Carmona 001; Jordi Cortadella; Michael Kishinevsky; Alexander Taubin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Guest Editorial: Special Section on Asynchronous Circuits and Systems. - Jordi Cortadella; Alexander Taubin (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Automatic microarchitectural pipelining. - Marc Galceran Oms; Jordi Cortadella; Dmitry Bufistov; Michael Kishinevsky (DATE, 2010)

Symbolic performance analysis of elastic systems. - Marc Galceran Oms; Jordi Cortadella; Michael Kishinevsky (ICCAD, 2010)

Elastic systems. - Jordi Cortadella; Marc Galceran Oms; Michael Kishinevsky (MEMOCODE, 2010)

Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing. - Nikita Nikitin; Satrajit Chatterjee; Jordi Cortadella; Michael Kishinevsky; Ümit Y. Ogras (NOCS, 2010)

Process Mining Meets Abstract Interpretation. - Josep Carmona 001; Jordi Cortadella (ECML/PKDD (1), 2010)

On the Performance Evaluation of Multi-Guarded Marked Graphs with Single-Server Semantics. - Jorge Júlvez; Jordi Cortadella; Michael Kishinevsky (Discret. Event Dyn. Syst., 2010)

New Region-Based Algorithms for Deriving Bounded Petri Nets. - Josep Carmona 001; Jordi Cortadella; Michael Kishinevsky (IEEE Trans. Computers, 2010)

A Scheduling Strategy for Synchronous Elastic Designs. - Josep Carmona 001; Jorge Júlvez; Jordi Cortadella; Michael Kishinevsky (Fundam. Informaticae, 2011)

Microarchitectural Transformations Using Elasticity. - Marc Galceran Oms; Alexander Gotmanov; Jordi Cortadella; Michael Kishinevsky (ACM J. Emerg. Technol. Comput. Syst., 2011)

Static Task Mapping for Tiled Chip Multiprocessors with Multiple Voltage Islands. - Nikita Nikitin; Jordi Cortadella (ARCS, 2012)

Analytical Performance Modeling of Hierarchical Interconnect Fabrics. - Nikita Nikitin; Javier de San Pedro; Josep Carmona 001; Jordi Cortadella (NOCS, 2012)

Integrating formal verification in an online judge for e-Learning logic circuit design. - Javier de San Pedro; Josep Carmona 001; Jordi Cortadella; Jordi Petit (SIGCSE, 2012)

Physical-aware system-level design for tiled hierarchical chip multiprocessors. - Jordi Cortadella; Javier de San Pedro; Nikita Nikitin; Jordi Petit (ISPD, 2013)

Physical planning for the architectural exploration of large-scale chip multiprocessors. - Javier de San Pedro; Nikita Nikitin; Jordi Cortadella; Jordi Petit (NOCS, 2013)

Brownian Circuits: Fundamentals. - Ferdinand Peper; Jia Lee; Josep Carmona 001; Jordi Cortadella; Kenichi Morita (ACM J. Emerg. Technol. Comput. Syst., 2013)

Area-Optimal Transistor Folding for 1-D Gridded Cell Design. - Jordi Cortadella (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Architectural Exploration of Large-Scale Hierarchical Chip Multiprocessors. - Nikita Nikitin; Javier de San Pedro; Jordi Cortadella (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Metastability in Better-Than-Worst-Case Designs. - Salomon Beer; Marco Cannizzaro; Jordi Cortadella; Ran Ginosar; Luciano Lavagno (ASYNC, 2014)

Hardware primitives for the synthesis of multithreaded elastic systems. - Giorgos Dimitrakopoulos; I. Seitanidis; Anastasios Psarras; K. Tsiouris; Pavlos M. Mattheakis; Jordi Cortadella (DATE, 2014)

A hierarchical approach for generating regular floorplans. - Javier de San Pedro; Jordi Cortadella; Antoni Roca 001 (ICCAD, 2014)

A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing. - Jordi Cortadella; Jordi Petit; Sergio Gómez; Francesc Moll (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Process Discovery Algorithms Using Numerical Abstract Domains. - Josep Carmona 001; Jordi Cortadella (IEEE Trans. Knowl. Data Eng., 2014)

A retargetable and accurate methodology for logic-IP-internal electromigration assessment. - Palkesh Jain; Sachin S. Sapatnekar; Jordi Cortadella (ASP-DAC, 2015)

Log-Based Simplification of Process Models. - Javier de San Pedro; Josep Carmona 001; Jordi Cortadella (BPM, 2015)

Reactive clocks with variability-tracking jitter. - Jordi Cortadella; Luciano Lavagno; Pedro Lopez; Marc Lupon; Alberto Moreno; Antoni Roca 001; Sachin S. Sapatnekar (ICCD, 2015)

Stochastic and topologically aware electromigration analysis for clock skew. - Palkesh Jain; Sachin S. Sapatnekar; Jordi Cortadella (IRPS, 2015)

RTL Synthesis: From Logic Synthesis to Automatic Pipelining. - Jordi Cortadella; Marc Galceran Oms; Michael Kishinevsky; Sachin S. Sapatnekar (Proc. IEEE, 2015)

SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits. - Marco Cannizzaro; Salomon Beer; Jordi Cortadella; Ran Ginosar; Luciano Lavagno (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Ring Oscillator Clocks and Margins. - Jordi Cortadella; Marc Lupon; Alberto Moreno; Antoni Roca 001; Sachin S. Sapatnekar (ASYNC, 2016)

Specification Mining for Asynchronous Controllers. - Javier de San Pedro; Thomas Bourgeat; Jordi Cortadella (ASYNC, 2016)

Discovering Duplicate Tasks in Transition Systems for the Simplification of Process Models. - Javier de San Pedro; Jordi Cortadella (BPM, 2016)

Mining structured petri nets for the visualization of process behavior. - Javier de San Pedro; Jordi Cortadella (SAC, 2016)

A Fast and Retargetable Framework for Logic-IP-Internal Electromigration Assessment Comprehending Advanced Waveform Effects. - Palkesh Jain; Jordi Cortadella; Sachin S. Sapatnekar (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Process Windows. - Andrey Mokhov; Jordi Cortadella; Alessandro de Gennaro (ACSD, 2017)

A hierarchical mathematical model for automatic pipelining and allocation using elastic systems. - Jordi Cortadella; Jordi Petit (ACSSC, 2017)

Waveform Transition Graphs: A Designer-Friendly Formalism for Asynchronous Behaviours. - Jordi Cortadella; Alberto Moreno; Danil Sokolov; Alex Yakovlev; David Lloyd (ASYNC, 2017)

Synthesis of All-Digital Delay Lines. - Alberto Moreno; Jordi Cortadella (ASYNC, 2017)

Boolean Decomposition for AIG Optimization. - Lucas Machado; Jordi Cortadella (ACM Great Lakes Symposium on VLSI, 2017)

Under-the-Cell Routing to Improve Manufacturability. - Alex Vidal-Obiols; Jordi Cortadella; Jordi Petit (ACM Great Lakes Symposium on VLSI, 2017)

Voltage Noise Analysis with Ring Oscillator Clocks. - Lucas Machado; Antoni Roca Perez; Jordi Cortadella (ISVLSI, 2017)

State Encoding of Asynchronous Controllers Using Pseudo-Boolean Optimization. - Alberto Moreno; Jordi Cortadella (ASYNC, 2018)

State-Based Encoding of Large Asynchronous Controllers. - Alberto Moreno; Jordi Cortadella (IEEE Access, 2018)

Jutge.org: Characteristics and Experiences. - Jordi Petit; Salvador Roura; Josep Carmona 001; Jordi Cortadella; Jordi Duch; Omer Giménez; Anaga Mani; Jan Mas; Enric Rodríguez-Carbonell; Enric Rubio; Enric de San Pedro; Divya Venkataramani (IEEE Trans. Learn. Technol., 2018)

From Nets to Circuits and from Circuits to Nets. - Jordi Cortadella (Carl Adam Petri: Ideas, Personality, Impact, 2019)

Synthesis from Waveform Transition Graphs. - Alberto Moreno; Danil Sokolov; Jordi Cortadella (ASYNC, 2019)

Exact and Heuristic Allocation of Multi-kernel Applications to Multi-FPGA Platforms. - Junnan Shan; Mario R. Casu; Jordi Cortadella; Luciano Lavagno; Mihai T. Lazarescu (DAC, 2019)

RTL-Aware Dataflow-Driven Macro Placement. - Alex Vidal-Obiols; Jordi Cortadella; Jordi Petit; Marc Galceran Oms; Ferran Martorell (DATE, 2019)

Corrections to "Jutge.org: Characteristics and Experiences". - Jordi Petit; Salvador Roura; Josep Carmona 001; Jordi Cortadella; Jordi Duch; Omer Giménez; Anaga Mani; Jan Mas; Enric Rodríguez-Carbonell; Enric Rubio; Enric de San Pedro; Divya Venkataramani (IEEE Trans. Learn. Technol., 2019)

Computing the full quotient in bi-decomposition by approximation. - Anna Bernasconi 001; Valentina Ciriani; Jordi Cortadella; Tiziano Villa (DATE, 2020)

Transistor Placement for Automatic Cell Synthesis through Boolean Satisfiability. - Maicon Schneider Cardoso; Andrei A. O. Bubolz; Jordi Cortadella; Leomar Rosa; Felipe S. Marques 001 (ISCAS, 2020)

Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches. - Juan Segarra; Jordi Cortadella; Ruben Gran Tejero; Víctor Viñals Yúfera (IEEE Access, 2020)

Support-Reducing Decomposition for FPGA Mapping. - Lucas Machado; Jordi Cortadella (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Power-Optimal Mapping of CNN Applications to Cloud-Based Multi-FPGA Platforms. - Junnan Shan; Mihai T. Lazarescu; Jordi Cortadella; Luciano Lavagno; Mario R. Casu (IEEE Trans. Circuits Syst., 2020)

Decomposition of transition systems into sets of synchronizing state machines. - Viktor Teren; Jordi Cortadella; Tiziano Villa (DSD, 2021)

CNN-on-AWS: Efficient Allocation of Multikernel Applications on Multi-FPGA Platforms. - Junnan Shan; Mihai T. Lazarescu; Jordi Cortadella; Luciano Lavagno; Mario R. Casu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Multilevel Dataflow-Driven Macro Placement Guided by RTL Structure and Analytical Methods. - Alex Vidal-Obiols; Jordi Cortadella; Jordi Petit; Marc Galceran Oms; Ferran Martorell (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Decomposition of transition systems into sets of synchronizing Free-choice Petri Nets. - Viktor Teren; Jordi Cortadella; Tiziano Villa (DSD, 2022)

Fast Energy-Optimal Multikernel DNN-Like Application Allocation on Multi-FPGA Platforms. - Junnan Shan; Mihai T. Lazarescu; Jordi Cortadella; Luciano Lavagno; Mario R. Casu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Buffer Placement and Sizing for High-Performance Dataflow Circuits. - Lana Josipovic; Shabnam Sheikhha; Andrea Guerrieri; Paolo Ienne; Jordi Cortadella (ACM Trans. Reconfigurable Technol. Syst., 2022)

Seto: A Framework for the Decomposition of Petri Nets and Transition Systems. - Viktor Teren; Jordi Cortadella; Tiziano Villa (DSD, 2023)

Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking. - Jiahui Xu; Emmet Murphy; Jordi Cortadella; Lana Josipovic (FPGA, 2023)

Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops. - Filippo Minnella; Jordi Cortadella; Mario R. Casu; Mihai T. Lazarescu; Luciano Lavagno (IEEE Access, 2023)

Generation of synchronizing state machines from a transition system: A region-based approach. - Viktor Teren; Jordi Cortadella; Tiziano Villa (Int. J. Appl. Math. Comput. Sci., 2023)

Mix & Latch: Comparison With State-of-the-Art Retiming on a RISC-V Benchmark. - Lorenzo Lagostina; Filippo Minnella; Jordi Cortadella; Mario R. Casu; Mihai T. Lazarescu; Luciano Lavagno (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Area-driven Boolean bi-decomposition by function approximation. - Anna Bernasconi 001; Valentina Ciriani; Jordi Cortadella; Marco Costa; Tiziano Villa (ACM Trans. Design Autom. Electr. Syst., 2025)