MEM: A new execution model for Prolog. - Jordi Tubella; Antonio González 001 (Microprocess. Microprogramming, 1993)

Combining depth-first and breadth-first search in Prolog execution. - Jordi Tubella; Antonio González 001 (GULP-PRODE (2), 1994)

A Partial Breadth-First Execution Model for Prolog. - Jordi Tubella; Antonio González 001 (ICTAI, 1994)

The Multipath Parallel Execution Model for Prolog. - Antonio González 001; Jordi Tubella (PASCO, 1994)

Exploiting path parallelism in logic programming. - Jordi Tubella; Antonio González 001 (PDP, 1995)

The Multipath Architecture for Prolog Programs. - Jordi Tubella; Antonio González 001; E. Elias (Comput. J., 1996)

Multipath: un sistema para la programación lógica. - Jordi Tubella (1996)

Control Speculation in Multithreaded Processors through Dynamic Loop Detection. - Jordi Tubella; Antonio González 001 (HPCA, 1998)

Speculative Multithreaded Processors. - Pedro Marcuello; Antonio González 001; Jordi Tubella (International Conference on Supercomputing, 1998)

Reducing Memory Traffic Via Redundant Store Instructions. - Carlos Molina; Antonio González 001; Jordi Tubella (HPCN Europe, 1999)

Trace-Level Reuse. - Antonio González 001; Jordi Tubella; Carlos Molina (ICPP, 1999)

Dynamic removal of redundant computations. - Carlos Molina; Antonio González 001; Jordi Tubella (International Conference on Supercomputing, 1999)

Value Prediction for Speculative Multithreaded Architectures. - Pedro Marcuello; Jordi Tubella; Antonio González 001 (MICRO, 1999)

Trace-Level Speculative Multithreaded Architecture. - Carlos Molina; Antonio González 001; Jordi Tubella (ICCD, 2002)

Value Compression to Reduce Power in Data Caches. - Carles Aliagas; Carlos Molina; Montse Garcia 002; Antonio González 001; Jordi Tubella (Euro-Par, 2003)

Non redundant data cache. - Carlos Molina; Carles Aliagas; Montse Garcia 002; Antonio González 001; Jordi Tubella (ISLPED, 2003)

Thread Partitioning and Value Prediction for Exploiting Speculative Thread-Level Parallelism. - Pedro Marcuello; Antonio González 001; Jordi Tubella (IEEE Trans. Computers, 2004)

Compiler analysis for trace-level speculative multithreaded architectures. - Carlos Molina; Antonio González 001; Jordi Tubella (Interaction between Compilers and Computer Architectures, 2005)

Reducing Misspeculation Penalty in Trace-Level Speculative Multithreaded Architectures. - Carlos Molina; Jordi Tubella; Antonio González 001 (ISHPC, 2005)

A Performance and Area Efficient Architecture for Intrusion Detection Systems. - Govind Sreekar Shenoy; Jordi Tubella; Antonio González 001 (IPDPS, 2011)

Hardware/Software Mechanisms for Protecting an IDS against Algorithmic Complexity Attacks. - Govind Sreekar Shenoy; Jordi Tubella; Antonio González 001 (IPDPS Workshops, 2012)

Exploiting temporal locality in network traffic using commodity multi-cores. - Govind Sreekar Shenoy; Jordi Tubella; Antonio González 001 (ISPASS, 2012)

Improving the Performance Efficiency of an IDS by Exploiting Temporal Locality in Network Traffic. - Govind Sreekar Shenoy; Jordi Tubella; Antonio González 001 (MASCOTS, 2012)

Improving the Resilience of an IDS against Performance Throttling Attacks. - Govind Sreekar Shenoy; Jordi Tubella; Antonio González 001 (SecureComm, 2012)

Chrysso: an integrated power manager for constrained many-core processors. - Sudhanshu Shekhar Jha; Wim Heirman; Ayose Falcón; Trevor E. Carlson; Kenzo Van Craeynest; Jordi Tubella; Antonio González 001; Lieven Eeckhout (Conf. Computing Frontiers, 2015)

An Ultra Low-Power Hardware Accelerator for Acoustic Scoring in Speech Recognition. - Hamid Tabani; José-María Arnau; Jordi Tubella; Antonio González 001 (PACT, 2017)

Shared resource aware scheduling on power-constrained tiled many-core processors. - Sudhanshu Shekhar Jha; Wim Heirman; Ayose Falcón; Jordi Tubella; Antonio González 001; Lieven Eeckhout (J. Parallel Distributed Comput., 2017)

A Novel Register Renaming Technique for Out-of-Order Processors. - Hamid Tabani; José-María Arnau; Jordi Tubella; Antonio González 001 (HPCA, 2018)

Performance Analysis and Optimization of Automatic Speech Recognition. - Hamid Tabani; José-María Arnau; Jordi Tubella; Antonio González 001 (IEEE Trans. Multi Scale Comput. Syst., 2018)

Lightweight Register File Caching in Collector Units for GPUs. - Mojtaba Abaie Shoushtary; José-María Arnau; Jordi Tubella Murgadas; Antonio González 001 (GPGPU@PPoPP, 2023)

A Lightweight, Compiler-Assisted Register File Cache for GPGPU. - Mojtaba Abaie Shoushtary; José-María Arnau; Jordi Tubella Murgadas; Antonio González 001 (CoRR, 2023)

Memento: An Adaptive, Compiler-Assisted Register File Cache for GPUs. - Mojtaba Abaie Shoushtary; José-María Arnau; Jordi Tubella Murgadas; Antonio González 001 (ISCA, 2024)

Control Flow Management in Modern GPUs. - Mojtaba Abaie Shoushtary; Jordi Tubella Murgadas; Antonio González 001 (CoRR, 2024)