A New Approach to Multiplexer Minimisation in the CALLAS Synthesis Environment. - Norbert Wehn; Jörg Biesenack; Michael Pilsl (VLSI, 1991)

Flexible timing specification in a VHDL synthesis subset. - A. Stoll; Jörg Biesenack; Steffen Rumler (EURO-DAC, 1992)

Data Part Optimizations in the CALLAS Synthesis Environment. - Jörg Biesenack; Norbert Wehn; A. Stoll; Michael Payer (Synthesis for Control Dominated Circuits, 1992)

The Siemens high-level synthesis system CALLAS. - Jörg Biesenack; Michael Koster; Anton Langmaier; Stephane Ledeux; Sabine März; Michael Payer; Michael Pilsl; Steffen Rumler; Holger Soukup; Norbert Wehn; Peter Duzy (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Scheduling of behavioral VHDL by retiming techniques. - Norbert Wehn; Jörg Biesenack; Peter Duzy; T. Langmaier; Michael Münch; Michael Pilsl; Steffen Rumler (EURO-DAC, 1994)