Cell Signal Measurement for High-Density DRAMs. - Jörg E. Vollrath (ITC, 1997)

Power Analysis of DRAMs. - Jörg E. Vollrath; Markus Huebl; Ernst Stahl (Asian Test Symposium, 1998)

Tutorial: Characterizing SDRAMS. - Jörg E. Vollrath (MTDT, 1999)

Synchronous Dynamic Memory Test Construction: A Field Approach. - Jörg E. Vollrath (MTDT, 2000)

Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment. - Jörg E. Vollrath; Randall Rooney (ITC, 2001)

Compressed Bit Fail Maps for Memory Fail Pattern Classification. - Jörg E. Vollrath; Ulf Lederer; Thomas Hladschik (J. Electron. Test., 2001)

Signal Margin Analysis for Memory Sense Amplifiers . - Jörg E. Vollrath (DELTA, 2002)

Output Timing Measurement Using an Idd Method. - Jörg E. Vollrath (MTDT, 2003)

Testing and Characterization of SDRAMs. - Jörg E. Vollrath (IEEE Des. Test Comput., 2003)

Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach. - Zaid Al-Ars; Said Hamdioui; Jörg E. Vollrath (Asian Test Symposium, 2005)

DRAM-Specific Space of Memory Tests. - Zaid Al-Ars; Said Hamdioui; Ad J. van de Goor; Georgi Gaydadjiev; Jörg E. Vollrath (ITC, 2006)

DDR2 DRAM Output Timing Optimization. - Jörg E. Vollrath; Jürg Schwizer; Marcin Gnat; Ralf Schneider; Bret Johnson (MTDT, 2006)

Using models, simulation and measurements for teaching circuit design. - Jörg E. Vollrath (EDUCON, 2013)

Interactive tools for teaching electrical engineering. - Jörg E. Vollrath (EDUCON, 2014)

An open access minimum automatic task generation live feedback system for electrical engineering. - Jörg E. Vollrath (EDUCON, 2015)

Open Access Microelectronics Course. - Jörg E. Vollrath (EWME, 2018)