Design of parallel preprocessing image sensors. - Jörg Schreiter; Rico Srowik; Achim Graupner; Stefan Getzlaff; René Schüffny (KES, 1999)

A system-on-chip realization of a CMOS image sensor with programmable analog image preprocessing. - Stefan Getzlaff; Jörg Schreiter; Achim Graupner; René Schüffny (ISCAS (4), 2001)

Minimizing charge injection errors in high-precision, high-speed SC-circuits. - Jörg Krupar; Rico Srowik; Jörg Schreiter; Achim Graupner; René Schüffny; Udo Jörges (ISCAS (1), 2001)

A vision device for image processing. - Achim Graupner; Stefan Getzlaff; Jörg Schreiter; René Schüffny (SIP, 2001)

An Analog VLSI Pulsed Neural Network for Image Segmentation Using Adaptive Connection Weights. - Arne Heittmann; Ulrich Ramacher; Daniel Matolin; Jörg Schreiter; René Schüffny (ICANN, 2002)

Analog implementation for networks of integrate-and-fire neurons with adaptive local connectivity. - Jörg Schreiter; Ulrich Ramacher; Arne Heittmann; D. Matolini; René Schüffny (NNSP, 2002)

High resolution ADPLL frequency synthesizer for FPGA-and ASIC-based applications. - Riad Stefo; Jörg Schreiter; Jens-Uwe Schluessler; René Schüffny (FPT, 2003)

CMOS image sensor with mixed-signal processor array. - Achim Graupner; Jörg Schreiter; Stefan Getzlaff; René Schüffny (IEEE J. Solid State Circuits, 2003)

Pulse coupled neural networks with adaptive synapses for image segmentation. - Jörg Schreiter; Ulrich Ramacher; Arne Heittmann; Daniel Matolin; René Schüffny (ARCS Workshops, 2004)

Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation. - Jörg Schreiter; Ulrich Ramacher; Arne Heittmann; Daniel Matolin; René Schüffny (Image Processing: Algorithms and Systems, 2004)

An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation. - Daniel Matolin; Jörg Schreiter; Stefan Getzlaff; René Schüffny (PARELEC, 2004)

An MPSoC for energy-efficient database query processing. - Sebastian Haas; Oliver Arnold; Benedikt Nöthen; Stefan Scholze; Georg Ellguth; Andreas Dixius; Sebastian Höppner; Stefan Schiefer; Stephan Hartmann 002; Stephan Henker; Thomas Hocker; Jörg Schreiter; et al. (DAC, 2016)

How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC. - Sebastian Höppner; Jörg Schreiter; Robert Niebsch; Stephan Scherzer; Ulrich Hensel; Jörg Winkler; Mario Orgis; Holger Eisenreich; Dennis Walter; Uwe Steeb; André Scharfe; Clifford Dmello; et al. (ESSDERC, 2019)

A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM. - Dennis Walter; André Scharfe; Alexander Oefelein; Florian Schraut; Heiner Bauer; Farkas Csaszar; Robert Niebsch; Jörg Schreiter; Holger Eisenreich; Sebastian Höppner (COOL CHIPS, 2020)

Method for the Computer-Aided Schematic Design and Simulation of Hydrogel-Based Microfluidic Systems. - Andreas Voigt; Jörg Schreiter; Philipp Frank; Cesare Pini; Christian Mayr 001; Andreas Richter 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology. - Sebastian Höppner; Holger Eisenreich; Dennis Walter; André Scharfe; Alexander Oefelein; Florian Schraut; Jörg Schreiter; Thorsten Riedel; Heiner Bauer; Robert Niebsch; Stephan Scherzer; Thomas Hocker; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2020)