Architecture of an Adaptive Test System Built on FPGAs. - Jörg Sachße; Heinz-Dietrich Wuttke; Steffen Ostendorff; Jorge H. Meza Escobar (ARCS, 2011)

Automatic generation of an FPGA based embedded test system for printed circuit board testing. - Jorge H. Meza Escobar; J. SachBe; Steffen Ostendorff; Heinz-Dietrich Wuttke (LATW, 2012)

Localization of Bugs in Processor Designs Using zamiaCAD Framework. - Anton Tsepurov; Valentin Tihhomirov; Maksim Jenihhin; Jaan Raik; Gunter Bartsch; Jorge Hernán Meza Escobar; Heinz-Dietrich Wuttke (MTV, 2012)

ISA configurability of an FPGA test-processor used for board-level interconnection testing. - Jorge H. Meza Escobar; Jörg Sachße; Steffen Ostendorff; Heinz-Dietrich Wuttke (LATW, 2013)

Modeling timing constraints for automatic generation of embedded test instruments. - Steffen Ostendorff; Jorge H. Meza Escobar; Heinz-Dietrich Wuttke; Thomas Sasse; Sebastian Richter (DDECS, 2014)

Automated Design Error Localization in RTL Designs. - Maksim Jenihhin; Anton Tsepurov; Valentin Tihhomirov; Jaan Raik; Hanno Hantson; Raimund Ubar; Gunter Bartsch; Jorge Hernán Meza Escobar; Heinz-Dietrich Wuttke (IEEE Des. Test, 2014)

A Configurable Test-Processor for Board-Level Testing. - Jorge H. Meza Escobar; Heinz-Dietrich Wuttke; Steffen Ostendorff (DSD, 2016)

Towards an embedded board-level tester: study of a configurable test processor. - Jorge Hernán Meza Escobar (2017)