Inertial and degradation delay model for CMOS logic gates. - Jorge Juan-Chico; Paulino Ruiz-de-Clavijo; Manuel J. Bellido; Antonio J. Acosta 001; Manuel Valencia 001 (ISCAS, 2000)

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. - Antonio J. Acosta 001; Raúl Jiménez; Jorge Juan-Chico; Manuel J. Bellido; Manuel Valencia-Barrero (PATMOS, 2000)

Degradation Delay Model Extension to CMOS Gates. - Jorge Juan-Chico; Manuel J. Bellido; Paulino Ruiz-de-Clavijo; Antonio J. Acosta 001; Manuel Valencia-Barrero (PATMOS, 2000)

HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. - Paulino Ruiz-de-Clavijo; Jorge Juan-Chico; Manuel J. Bellido; Antonio J. Acosta 001; Manuel Valencia-Barrero (DATE, 2001)

AUTODDM: automatic characterization tool for the delay degradation model. - Jorge Juan-Chico; Manuel J. Bellido; Paulino Ruiz-de-Clavijo; Carmen Baena Oliva; Manuel Valencia 001 (ICECS, 2001)

Gate-level simulation of CMOS circuits using the IDDM model. - Manuel J. Bellido; Jorge Juan-Chico; Paulino Ruiz-de-Clavijo; Antonio J. Acosta 001; Manuel Valencia-Barrero (ISCAS (5), 2001)

Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. - Carmen Baena Oliva; Jorge Juan-Chico; Manuel J. Bellido; Paulino Ruiz-de-Clavijo; Carlos Jesús Jiménez-Fernández; Manuel Valencia 001 (PATMOS, 2002)

Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). - Alejandro Millán 001; Jorge Juan-Chico; Manuel J. Bellido; Paulino Ruiz-de-Clavijo; David Guerrero Martos (PATMOS, 2002)

Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. - Paulino Ruiz-de-Clavijo; Jorge Juan-Chico; Manuel J. Bellido; Alejandro Millán 001; David Guerrero Martos (PATMOS, 2002)

Internode: Internal Node Logic Computational Model. - Alejandro Millán 001; Manuel J. Bellido; Jorge Juan-Chico; David Guerrero Martos; Paulino Ruiz-de-Clavijo; Enrique Ostúa (Annual Simulation Symposium, 2003)

Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. - David Guerrero Martos; Gustavo Wilke; José Luís Almada Güntzel; Manuel J. Bellido; Jorge Juan-Chico; Paulino Ruiz-de-Clavijo; Alejandro Millán 001 (PATMOS, 2003)

Signal Sampling Based Transition Modeling for Digital Gates Characterization. - Alejandro Millán 001; Jorge Juan-Chico; Manuel J. Bellido; Paulino Ruiz-de-Clavijo; David Guerrero Martos; Enrique Ostúa (PATMOS, 2004)

Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. - Alejandro Millán Calderón; Manuel Jesús Bellido Díaz; Jorge Juan-Chico; Paulino Ruiz-de-Clavijo; David Guerrero Martos; Enrique Ostúa; Julian Viejo (PATMOS, 2005)

Logic-Level Fast Current Simulation for Digital CMOS Circuits. - Paulino Ruiz-de-Clavijo; Jorge Juan-Chico; Manuel Jesús Bellido Díaz; Alejandro Millán Calderón; David Guerrero Martos; Enrique Ostúa; Julian Viejo (PATMOS, 2005)

Accurate Logic-Level Current Estimation for Digital CMOS Circuits. - Paulino Ruiz-de-Clavijo; Jorge Juan-Chico; Manuel Jesús Bellido Díaz; Alejandro Millán 001; David Guerrero Martos; Enrique Ostúa; Julian Viejo (J. Low Power Electron., 2006)

Static Power Consumption in CMOS Gates Using Independent Bodies. - David Guerrero Martos; Alejandro Millán 001; Jorge Juan-Chico; Manuel J. Bellido; Paulino Ruiz-de-Clavijo; Enrique Ostúa; Julian Viejo (PATMOS, 2007)

Improving the Performance of Static CMOS Gates by Using Independent Bodies. - David Guerrero Martos; Alejandro Millán 001; Jorge Juan-Chico; Manuel Jesús Bellido Díaz; Paulino Ruiz-de-Clavijo; Enrique Ostúa; Julian Viejo (J. Low Power Electron., 2007)

Using the complement of the cosine to compute trigonometric functions. - David Guerrero Martos; Alejandro Millán Calderón; Jorge Juan-Chico; Julian Viejo; Manuel Jesús Bellido Díaz; Paulino Ruiz-de-Clavijo; Enrique Ostúa (EURASIP J. Adv. Signal Process., 2020)

Address-encoded byte order. - David Guerrero Martos; German Cano-Quiveu; Jorge Juan-Chico; Alejandro Millán 001; Manuel J. Bellido; Julian Viejo; Paulino Ruiz-de-Clavijo; Enrique Ostúa (Microprocess. Microsystems, 2020)

An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation. - German Cano-Quiveu; Paulino Ruiz-De-Clavijo-Vazquez; Manuel Jesús Bellido Díaz; David Guerrero Martos; Julian Viejo-Cortes; Jorge Juan-Chico (IEEE Access, 2021)

IRIS: An embedded secure boot for IoT devices. - German Cano-Quiveu; Paulino Ruiz-De-Clavijo-Vazquez; Manuel Jesús Bellido Díaz; Jorge Juan-Chico; Julian Viejo-Cortes (Internet Things, 2023)