Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements. - Julian Viejo; Manuel J. Bellido; Alejandro Millán 001; Enrique Ostúa; Jorge Juan; Paulino Ruiz-de-Clavijo; David Guerrero Martos (IES, 2006)

Design of a FFT/IFFT module as an IP core suitable for embedded systems. - Julian Viejo; Alejandro Millán 001; Manuel J. Bellido; Jorge Juan; Paulino Ruiz-de-Clavijo; David Guerrero Martos; Enrique Ostúa; Alejandro Muñoz (SIES, 2007)

Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. - Alejandro Millán 001; Jorge Juan; Manuel J. Bellido; David Guerrero Martos; Paulino Ruiz-de-Clavijo; Julian Viejo (PATMOS, 2008)

Efficient techniques and methodologies for embedded system design usign free hardware and open standards. - Jose Ignacio Villar; Jorge Juan; Manuel J. Bellido (FPL, 2009)

Design and implementation of a suitable core for on-chip long-term verification. - Julian Viejo; Jose Ignacio Villar; Jorge Juan; Alejandro Millán 001; Manuel Jesús Bellido Díaz; Enrique Ostúa (SIES, 2010)

Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies. - Alejandro Millán 001; Manuel J. Bellido; Jorge Juan; David Guerrero Martos; Paulino Ruiz-de-Clavijo; Julian Viejo (J. Low Power Electron., 2010)

Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells. - David Guerrero Martos; Alejandro Millán 001; Jorge Juan; Manuel J. Bellido; Paulino Ruiz-de-Clavijo; Enrique Ostúa; Julian Viejo (J. Low Power Electron., 2011)

Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation. - Julian Viejo; Jorge Juan; Manuel Jesús Bellido Díaz; Alejandro Millán 001; Paulino Ruiz-de-Clavijo (IEEE Trans. Instrum. Meas., 2011)

Network Time Synchronization: A Full Hardware Approach. - Jorge Juan; Julian Viejo; Manuel J. Bellido (PATMOS, 2012)

Long-term on-chip verification of systems with logical events scattered in time. - Julian Viejo; Jose Ignacio Villar; Jorge Juan; Alejandro Millán 001; Enrique Ostúa; Juan Quiros (Microprocess. Microsystems, 2012)

Minimalistic SDHC-SPI hardware reader module for boot loader applications. - Paulino Ruiz-de-Clavijo; Enrique Ostúa; Manuel Jesús Bellido Díaz; Jorge Juan; Julian Viejo; David Guerrero Martos (Microelectron. J., 2017)