Design and verification of a layer-2 Ethernet MAC classification engine for a Gigabit Ethernet switch. - Jorge L. Tonfat; Ricardo Reis 001 (ICECS, 2010)

Functional verification of logic modules for a Gigabit Ethernet switch. - Jorge L. Tonfat; Gustavo Neuberger; Ricardo Reis 001 (LATW, 2011)

Soft-Error Probability Due to SET in Clock Tree Networks. - Raul Chipana; Eduardo Chielle; Fernanda Lima Kastensmidt; Jorge L. Tonfat; Ricardo Reis 001 (ISVLSI, 2012)

SET susceptibility estimation of clock tree networks from layout extraction. - Raul Chipana; Fernanda Lima Kastensmidt; Jorge L. Tonfat; Ricardo Reis 001 (LATW, 2012)

Using electromagnetic emanations for variability characterization in Flash-based FPGAs. - Jimmy Tarrillo; Jorge L. Tonfat; Fernanda Lima Kastensmidt; Ricardo Reis 001; Florent Bruguier; Morgan Bourree; Pascal Benoit; Lionel Torres (ISVLSI, 2013)

Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs. - Fernanda Lima Kastensmidt; Jorge L. Tonfat; Thiago Hanna Both; Paolo Rech; Gilson I. Wirth; Ricardo Reis 001; Florent Bruguier; Pascal Benoit; Lionel Torres; Christopher Frost 002 (ETS, 2014)

Soft error rate in SRAM-based FPGAs under neutron-induced and TID effects. - Lucas A. Tambara; Jorge L. Tonfat; Ricardo Reis 001; Fernanda Lima Kastensmidt; Evaldo Carlos Fonseca Pereira; Rafael Galhardo Vaz; Odair Lelis Goncalez (LATW, 2014)

Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs. - Fernanda Lima Kastensmidt; Jorge L. Tonfat; Thiago Hanna Both; Paolo Rech; Gilson I. Wirth; Ricardo Reis 001; Florent Bruguier; Pascal Benoit; Lionel Torres; Christopher Frost 002 (Microelectron. Reliab., 2014)

Energy efficient frame-level redundancy scrubbing technique for SRAM-based FPGAs. - Jorge L. Tonfat; Fernanda Lima Kastensmidt; Ricardo Reis 001 (AHS, 2015)

Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments. - Jimmy Tarrillo; Jorge L. Tonfat; Lucas A. Tambara; Fernanda Lima Kastensmidt; Ricardo Reis 001 (LATS, 2015)

Method to Analyze the Susceptibility of HLS Designs in SRAM-Based FPGAs Under Soft Errors. - Jorge L. Tonfat; Lucas A. Tambara; André Flores dos Santos; Fernanda Gusmão de Lima Kastensmidt (ARC, 2016)

Leakage current analysis in static CMOS logic gates for a transistor network design approach. - Jorge L. Tonfat; Guilherme Flach; Ricardo Reis 001 (PATMOS, 2016)

Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs. - André Flores dos Santos; Lucas Antunes Tambara; Fabio Benevenuti; Jorge L. Tonfat; Fernanda Lima Kastensmidt (ARC, 2017)

Soft error susceptibility analysis methodology of HLS designs in SRAM-based FPGAs. - Jorge L. Tonfat; Lucas A. Tambara; André Santos; Fernanda Lima Kastensmidt (Microprocess. Microsystems, 2017)

Experimental Applications on SRAM-Based FPGA for the NanosatC-BR2 Scientific Mission. - Fabio Benevenuti; Eduardo Chielle; Jorge L. Tonfat; Lucas A. Tambara; Fernanda Lima Kastensmidt; Carlos Alberto Zaffari; João Baptista dos Santos Martins; Otávio Santos Cupertino Durão (IPDPS Workshops, 2019)