An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains. - Jorge Luis Lagos-Benites; Davide Appello; Paolo Bernardi; Michelangelo Grosso; Danilo Ravotto; Edgar E. Sánchez; Matteo Sonza Reorda (DFT, 2007)

An FPGA-Emulation-Based Platform for Characterization of Digital Baseband Communication Systems. - Jorge Luis Lagos-Benites; Michelangelo Grosso; Matteo Sonza Reorda; G. Audisio; M. Pipponzi; Marco Sabatini; V. A. Avantaggiati (DFT, 2011)

A Low-Cost Emulation System for Fast Co-verification and Debug. - Jorge Luis Lagos-Benites; Michelangelo Grosso; Luca Sterpone; Matteo Sonza Reorda; G. Audisio; M. Pipponzi; Marco Sabatini (ETS, 2011)

On-line software-based self-test of the Address Calculation Unit in RISC processors. - Paolo Bernardi; Lyl M. Ciganda; Mauricio de Carvalho; Michelangelo Grosso; Jorge Luis Lagos-Benites; Ernesto Sánchez 001; Matteo Sonza Reorda; Oscar Ballan (ETS, 2012)

A versatile analog front-end for sensors based on piezoresistive silicon nanowire detection. - Olivier Leman; Antonios Nikas; Haiyan Zhou; Jorge-Luis Lagos 001; Bakul Jitendra Vinchhi; Johann Hauer; Guillaume Jourdan; Patrice Rey (ISCAS, 2015)

A 83dB SNDR low power readout ASIC for piezoresistive nanogauge based gyroscopes. - Antonios Nikas; Olivier Leman; Haiyan Zhou; Jorge-Luis Lagos 001; Bakul Jitendra Vinchhi; Johann Hauer (ISCAS, 2016)

A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers. - Jorge Lagos 001; Benjamin P. Hershberg; Ewout Martens; Piet Wambacq; Jan Craninckx (CICC, 2018)

A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion. - Benjamin P. Hershberg; Davide Dermit; Barend van Liempd; Ewout Martens; Nereo Markulic; Jorge Lagos 001; Jan Craninckx (ISSCC, 2019)

A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm. - Benjamin P. Hershberg; Barend van Liempd; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Davide Dermit; Jan Craninckx (ISSCC, 2019)

A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS. - Jorge Lagos 001; Benjamin P. Hershberg; Ewout Martens; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2019)

A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers. - Jorge Lagos 001; Benjamin P. Hershberg; Ewout Martens; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2019)

16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation. - Zihao Zheng; Lai Wei; Jorge Lagos 001; Ewout Martens; Yan Zhu 001; Chi-Hang Chan; Jan Craninckx; Rui Paulo Martins (ISSCC, 2020)

A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm. - Benjamin P. Hershberg; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Davide Dermit; Jan Craninckx (VLSI Circuits, 2020)

A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC. - Lucas Moura Santana; Ewout Martens; Jorge Lagos 001; Benjamin P. Hershberg; Piet Wambacq; Jan Craninckx (ESSCIRC, 2021)

A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS. - Jorge Lagos 001; Nereo Markulic; Benjamin P. Hershberg; Davide Dermit; Mithlesh Shrivas; Ewout Martens; Jan Craninckx (VLSI Circuits, 2021)

An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC. - Lai Wei; Zihao Zheng; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Yan Zhu 001; Chi-Hang Chan; Jan Craninckx; Rui Paulo Martins (VLSI Circuits, 2021)

A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion. - Benjamin P. Hershberg; Davide Dermit; Barend van Liempd; Ewout Martens; Nereo Markulic; Jorge Lagos 001; Jan Craninckx (IEEE J. Solid State Circuits, 2021)

A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm. - Benjamin P. Hershberg; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Davide Dermit; Jan Craninckx (IEEE J. Solid State Circuits, 2021)

Asynchronous Event-Driven Clocking and Control in Pipelined ADCs. - Benjamin P. Hershberg; Barend van Liempd; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Davide Dermit; Jan Craninckx (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS. - Jorge Lagos 001; Nereo Markulic; Benjamin P. Hershberg; Davide Dermit; Mithlesh Shrivas; Ewout Martens; Jan Craninckx (IEEE J. Solid State Circuits, 2022)

A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS. - Lucas Moura Santana; Ewout Martens; Jorge Lagos 001; Benjamin P. Hershberg; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2022)

A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier. - Zihao Zheng; Lai Wei; Jorge Lagos 001; Ewout Martens; Yan Zhu 001; Chi-Hang Chan; Jan Craninckx; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

Calibration Techniques for Optimizing Performance of High-Speed ADCs. - Ewout Martens; Nereo Markulic; Jorge Luis Lagos-Benites; Jan Craninckx (CICC, 2023)

A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS. - Lucas Moura Santana; Ewout Martens; Jorge Lagos 001; Piet Wambacq; Jan Craninckx (ESSCIRC, 2023)

A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration. - Lai Wei; Zihao Zheng; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Rui Paulo Martins; Yan Zhu 001; Jan Craninckx; Chi-Hang Chan (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC. - Ewout Martens; Adam Cooman; Pratap Tumkur Renukaswamy; Shun Nagata; Sehoon Park; Jorge-Luis Lagos 001; Nereo Markulic; Jan Craninckx (ISSCC, 2024)

A Single-Channel, 1-GS/s, 10.91-ENOB, 81-dB SFDR, 9.2-fJ/conv.-step, Ringamp-Based Pipelined ADC with Background Calibration in 16nm CMOS. - Jorge Lagos 001; Pratap Tumkur Renukaswamy; Nereo Markulic; Ewout Martens; Jan Craninckx (VLSI Technology and Circuits, 2024)

A 10GS/s Hierarchical Time-Interleaved ADC for RF-Sampling Applications. - Nereo Markulic; Johan Nguyen; Jorge Luis Lagos-Benites; Ewout Martens; Jan Craninckx (VLSI Technology and Circuits, 2024)