An integrated high resolution CMOS timing generator based on an array of delay locked loops. - Jorgen Christiansen (IEEE J. Solid State Circuits, 1996)

A four channel, self-calibrating, high resolution, time to digital converter. - Manuel Mota; Jorgen Christiansen (ICECS, 1998)

A high-resolution time interpolator based on a delay locked loop and an RC delay line. - Manuel Mota; Jorgen Christiansen (IEEE J. Solid State Circuits, 1999)

A fine time-resolution (<3 ps-rms) time-to-digital converter for highly integrated designs. - Lukas Perktold; Jorgen Christiansen (I2MTC, 2013)

A SystemVerilog-UVM Methodology for the Design, Simulation and Verification of Complex Readout Chips in High Energy Physics Applications. - Sara Marconi; Elia Conti; Pisana Placidi; Andrea Scorzoni; Jorgen Christiansen; Tomasz Hemperek (ApplePies, 2015)

Reusable SystemVerilog-UVM design framework with constrained stimuli modeling for High Energy Physics applications. - Sara Marconi; Elia Conti; Jorgen Christiansen; Pisana Placidi (ISSE, 2015)

A single-event upset robust, 2.2 GHz to 3.2 GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOS. - Jeffrey Prinzie; Michiel Steyaert; Paul Leroux; Jorgen Christiansen; Paulo Moreira (A-SSCC, 2016)