Rapid Embedded Hardware/Software System Generation. - Jorgen Peddersen; Seng Lin Shee; Andhi Janapsatya; Sri Parameswaran (VLSI Design, 2005)

CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time. - Jorgen Peddersen; Sri Parameswaran (ASP-DAC, 2007)

Energy Driven Application SelfAdaptation. - Jorgen Peddersen; Sri Parameswaran (VLSI Design, 2007)

Low-Impact Processor for Dynamic Runtime Power Management. - Jorgen Peddersen; Sri Parameswaran (IEEE Des. Test Comput., 2008)

Energy Driven Application Self-Adaptation at Run-time. - Jorgen Peddersen; Sri Parameswaran (J. Comput., 2008)

Run-time energy-driven optimisation of embedded systems: a complete solution. - Jorgen Peddersen (2008)

LOP: a novel SRAM-based architecture for low power and high throughput packet classification. - Xin He 002; Jorgen Peddersen; Sri Parameswaran (CODES+ISSS, 2009)

LOP_RE: Range encoding for low power packet classification. - Xin He 002; Jorgen Peddersen; Sri Parameswaran (LCN, 2009)

SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. - Mohammad Shihabul Haque; Jorgen Peddersen; Andhi Janapsatya; Sri Parameswaran (DAC, 2010)

DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. - Mohammad Shihabul Haque; Jorgen Peddersen; Andhi Janapsatya; Sri Parameswaran (DATE, 2010)

Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm. - Andhi Janapsatya; Aleksandar Ignjatovic; Jorgen Peddersen; Sri Parameswaran (DATE, 2010)

RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors. - Roshan G. Ragel; Jude Angelo Ambrose; Jorgen Peddersen; Sri Parameswaran (DIPES/BICC, 2010)

Improved Architectures for Range Encoding in Packet Classification System. - Xin He 002; Jorgen Peddersen; Sri Parameswaran (NCA, 2010)

ACS: Automatic Converter Synthesis for SoC Bus Protocols. - Karin Avnit; Arcot Sowmya; Jorgen Peddersen (TACAS, 2010)

LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM. - Xin He 002; Jorgen Peddersen; Sri Parameswaran (Des. Autom. Embed. Syst., 2010)

CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique. - Mohammad Shihabul Haque; Jorgen Peddersen; Sri Parameswaran (ICCAD, 2011)

Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction. - Su Myat Min; Jorgen Peddersen; Sri Parameswaran (VLSI Design, 2011)

A Rapid Methodology for Multi-mode Communication Circuit Generation. - Liang Tang; Jorgen Peddersen; Sri Parameswaran (VLSI Design, 2012)

DRMA: dynamically reconfigurable MPSoC architecture. - Lawrance Zhang; Jude Angelo Ambrose; Jorgen Peddersen; Sri Parameswaran; Roshan G. Ragel; Swarnalatha Radhakrishnan; Kewal K. Saluja (ACM Great Lakes Symposium on VLSI, 2013)

A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES. - Ankita Arora; Jude Angelo Ambrose; Jorgen Peddersen; Sri Parameswaran (ISVLSI, 2013)

SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs. - Jude Angelo Ambrose; Jorgen Peddersen; Sri Parameswaran; Alvin Labios; Yusuke Yachide (ASP-DAC, 2014)

A scorchingly fast FPGA-based Precise L1 LRU cache simulator. - Josef Schneider; Jorgen Peddersen; Sri Parameswaran (ASP-DAC, 2014)

MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis. - Josef Schneider; Jorgen Peddersen; Sri Parameswaran (DAC, 2014)

Speeding up single pass simulation of PLRUt caches. - Josef Schneider; Jorgen Peddersen; Sri Parameswaran (ASP-DAC, 2015)

E-pipeline: elastic hardware/software pipelines on a many-core fabric. - Xi Zhang 003; Haris Javaid; Muhammad Shafique 001; Jorgen Peddersen; Jörg Henkel; Sri Parameswaran (DATE, 2015)

Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications. - Jude Angelo Ambrose; Yusuke Yachide; Kapil Batra; Jorgen Peddersen; Sri Parameswaran (ICCD, 2015)

RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory. - Su Myat Min Shwe; Kapil Batra; Yusuke Yachide; Jorgen Peddersen; Sri Parameswaran (ICCD, 2015)

FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large Applications. - Vikkitharan Gnanasambandapillai; Jorgen Peddersen; Roshan G. Ragel; Sri Parameswaran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)