Performance of an experimental data flow architecture for signal processing. - Klaus Kronlöf; Jorma Skyttä; Iiro Hartimo; Olli Simula (ICASSP, 1982)

Utilization of VLSI for Creating an Active Data Base of 3-D Geometric Models. - Jorma Skyttä; Tapio Takala (Advances in Computer Graphics Hardware, 1986)

DFSP: A Data Flow Signal Processor. - Iiro Hartimo; Klaus Kronlöf; Olli Simula; Jorma Skyttä (IEEE Trans. Computers, 1986)

Partially Ordered Search Indices in the Organization of a Fixed Hierarchy. - Jorma Skyttä; Tapio Takala (Advances in Computer Graphics Hardware, 1987)

A Distributed Data Model for Raytracing. - Jorma Skyttä; Tapio Takala (Advances in Computer Graphics Hardware, 1988)

A new wireless paging network architecture. - Jarkko Vuori; J. Honkanen; Jorma Skyttä (PIMRC, 1994)

Implementation of a European paging system receiver using CORDIC algorithm. - Jarkko Vuori; Jorma Skyttä (EUSIPCO, 1996)

New Possibilities Offered by IPv6. - Mika Loukola; Jorma Skyttä (ICCCN, 1998)

Hop-by-hop option based flow-handling compared to other IP over ATM protocols. - Mika Loukola; Jorma Skyttä (PICS, 1998)

IPv6 over ATM flow-handling. - Mika Loukola; Jorma Skyttä (Comput. Commun., 1998)

Hardware Acceleration inside a Differentiated Services Access Node. - Juha Forsten; Mika Loukola; Jorma Skyttä (IDMS, 1999)

Dijkstra's Shortest Path Routing Algorithm in Reconfigurable Hardware. - Matti Tommiska; Jorma Skyttä (FPL, 2001)

Hardware-based adaptive general parameter extension in W-CDMA power control. - Matti Tommiska; Jarno M. A. Tanskanen; Jorma O. Skyttä (VTC Fall, 2001)

Enhanced Augmented IP Routing Protocol (EAIRP) in IPv6 Environment. - Mika Loukola; Jorma Skyttä (Electron. Commer. Res., 2001)

8 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm. - Antti Hämäläinen; Matti Tommiska; Jorma Skyttä (FPL, 2002)

A fully pipelined memoryless 17.8 Gbps AES-128 encryptor. - Kimmo U. Järvinen; Matti Tommiska; Jorma Skyttä (FPGA, 2003)

A VHDL Generator for Elliptic Curve Cryptography. - Kimmo U. Järvinen; Matti Tommiska; Jorma Skyttä (FPL, 2004)

A scalable architecture for elliptic curve point multiplication. - Kimmo Järvinen 001; Matti Tommiska; Jorma Skyttä (FPT, 2004)

FPGA-Based Implementation of a 59-Neuron Feedforward Neural Network with a 17.1 Gbps Interlayer Throughput. - Antti Hämäläinen; Matti Tommiska; Jorma Skyttä (IC-AI, 2004)

A Compact MD5 and SHA-1 Co-Implementation Utilizing Algorithm Similarities. - Kimmo U. Järvinen; Matti Tommiska; Jorma Skyttä (ERSA, 2005)

Hardware Implementation Analysis of the MD5 Hash Algorithm. - Kimmo U. Järvinen; Matti Tommiska; Jorma Skyttä (HICSS, 2005)

Efficient Circuitry for Computing τ-adic Non-Adjacent Form. - Kimmo Järvinen 001; Juha Forsten; Jorma Skyttä (ICECS, 2006)

FPGA Design of Self-certified Signature Verification on Koblitz Curves. - Kimmo U. Järvinen; Juha Forsten; Jorma Skyttä (CHES, 2007)

High-Speed Elliptic Curve Cryptography Accelerator for Koblitz Curves. - Kimmo U. Järvinen; Jorma O. Skyttä (FCCM, 2008)

On Parallelization of High-Speed Processors for Elliptic Curve Cryptography. - Kimmo U. Järvinen; Jorma Skyttä (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Fast point multiplication on Koblitz curves: Parallelization method and implementations. - Kimmo U. Järvinen; Jorma Skyttä (Microprocess. Microsystems, 2009)

How small and still effective a CMOS-SoC could ever be? - Hannu Heusala; Jorma Skyttä (NORCAS, 2015)