A testability strategy for multiprocessor architecture. - Francky Catthoor; Jos van Sas; Luc Inzé; Hugo De Man (IEEE Des. Test, 1989)

Cellular automata based self-test for programmable data paths. - Jos van Sas; Francky Catthoor; Hugo De Man (ITC, 1990)

Testability strategy and test pattern generation for register files and customized memories. - Jos van Sas; Francky Catthoor; Luc Inzé; Hugo De Man (Microprocess. Microsystems, 1990)

Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment. - Jos van Sas; Francky Catthoor; Peter Vandeput; Frank Rossaert; Hugo De Man (EURO-DAC, 1991)

Optimized BIST Strategies for Programmable Data Paths Based on Cellular Automata. - Jos van Sas; Francky Catthoor; Hugo De Man (ITC, 1992)

BIST for Embedded Static RAMs with Coverage Calculation. - Jos van Sas; Geert van Wauwe; Erik Huyskens; Dirk Rabaey (ITC, 1993)

Test Algorithms for Double-Buffered Random Access and Pointer-Addressed Memories. - Jos van Sas; Francky Catthoor; Hugo De Man (IEEE Des. Test Comput., 1993)

An Off-chip IDDQ Current Measurement Unit for Telecommunication ASICs. - Hans A. R. Manhaeve; Paul L. Wrighton; Jos van Sas; Urbain Swerts (ITC, 1994)

Design of a C-testable booth multiplier using a realistic fault model. - Jos van Sas; Chay Nowé; Didier Pollet; Francky Catthoor; Paul Vanoostende; Hugo De Man (J. Electron. Test., 1994)

Cellular automata based deterministic self-test strategies for programmable data paths. - Jos van Sas; Francky Catthoor; Hugo De Man (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Coping with Re-usability Using Sequential ATPG: A Practical Case Study. - Jos van Sas; Erik Huyskens; Hans Naert; Fred Schell; Ad J. van de Goor (ITC, 1995)

Towards an Effective IDDQ Test Vector Selection and Application Methodology. - Jos van Sas; Urbain Swerts; Marc Darquennes (ITC, 1996)