Timing optimization by an improved redundancy addition and removal technique. - Luis Entrena; Emilio Olías; Javier Uceda; José Alberto Espejo (EURO-DAC, 1996)

Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization. - Enrique San Millán; Luis Entrena; José Alberto Espejo; Silvia Chiusano; Fulvio Corno (DATE, 1999)

Logic Restructuring for MUX-Based FPGAs. - José Alberto Espejo; Luis Entrena; Enrique San Millán; Emilio Olías (EUROMICRO, 1999)

Functional extension of structural logic optimization techniques. - José Alberto Espejo; Luis Entrena; Enrique San Millán; Emilio Olías (ASP-DAC, 2001)

Generalized reasoning scheme for redundancy addition and removal logic optimization. - José Alberto Espejo; Luis Entrena; Enrique San Millán; Emilio Olías (DATE, 2001)

On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. - Enrique San Millán; Luis Entrena; José Alberto Espejo (DSD, 2001)

On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. - Enrique San Millán; Luis Entrena; José Alberto Espejo (ICCAD, 2001)

Logic Optimization of Unidirectional Circuits with Structural Methods. - Luis Entrena; Celia López; Emilio Olías; Enrique San Millán; José Alberto Espejo (IOLTW, 2001)

Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques. - Enrique San Millán; Luis Entrena; José Alberto Espejo; Celia López (J. Syst. Archit., 2003)

Logic Transformations by Multiple Wire Network Addition. - Enrique San Millán; Luis Entrena; José Alberto Espejo (DSD, 2008)