VHDL-AMS modeling of self-organizing neural systems. - José-Alejandro López Alcantud; Tom Kazmierski (ISCAS, 2000)

An Analogue Current-Mode Hardware Design Proposal for Preprocessing Layers in ART-Based Neural Networks. - José-Alejandro López Alcantud; José Ángel Díaz-Madrid; Hans Hauer; Ramón Ruiz Merino (IWANN (2), 2003)

Description and Simulation of Bio-inspired Systems Using VHDL-AMS. - Ginés Doménech-Asensi; José-Alejandro López Alcantud; Ramón Ruiz Merino (IWINAC (2), 2005)

Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem. - Ginés Doménech-Asensi; Juan Martínez-Alajarín; Ramón Ruiz Merino; José-Alejandro López Alcantud (FPL, 2006)

A fourth order CMOS band pass filter for PIR sensors. - Ginés Doménech-Asensi; F. Martinez-Viviente; J. Illade-Quinteiro; Juan Zapata-Pérez; Ramón Ruiz Merino; José-Alejandro López Alcantud; Juan Martínez-Alajarín; Francisco J. Fernández-Luque; Juan M. Carrillo; Miguel Angel Domínguez (ICECS, 2012)

An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation. - José Ángel Díaz-Madrid; Ginés Doménech-Asensi; José-Alejandro López Alcantud; M. Oberst (ISCAS, 2017)

An all-hardware implementation of the subpixel refinement stage in SIFT algorithm. - Pablo Rubio-Ibáñez; Ramón Ruiz Merino; Ginés Doménech-Asensi; J. Javier Martínez-Álvarez; Juan Zapata-Pérez; José Ángel Díaz-Madrid; José-Alejandro López Alcantud (Int. J. Circuit Theory Appl., 2018)

All-hardware SIFT implementation for real-time VGA images feature extraction. - Ginés Doménech-Asensi; Juan Zapata-Pérez; Ramón Ruiz Merino; José-Alejandro López Alcantud; José Ángel Díaz-Madrid; Víctor Manuel Brea Sánchez; Paula López 001 (J. Real Time Image Process., 2020)