An Analogue Current-Mode Hardware Design Proposal for Preprocessing Layers in ART-Based Neural Networks. - José-Alejandro López Alcantud; José Ángel Díaz-Madrid; Hans Hauer; Ramón Ruiz Merino (IWANN (2), 2003)

Current Mode CMOS Synthesis of a Motor-Control Neural System. - Ginés Doménech-Asensi; Ramón Ruiz Merino; Hans Hauer; José Ángel Díaz-Madrid (IWANN (2), 2003)

Improvement of ANNs Performance to Generate Fitting Surfaces for Analog CMOS Circuits. - José Ángel Díaz-Madrid; Pedro Monsalve-Campillo; Juan Hinojosa; María Victoria Rodellar Biarge; Ginés Doménech-Asensi (IWINAC (2), 2007)

Accurate and reusable macromodeling technique using a fuzzy-logic approach. - Ginés Doménech-Asensi; Juan Hinojosa; Ramón Ruiz Merino; José Ángel Díaz-Madrid (ISCAS, 2008)

Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing. - José Ángel Díaz-Madrid; Harald Neubauer; Hans Hauer; Ginés Doménech-Asensi; Ramón Ruiz Merino (DATE, 2009)

Fuzzy logic technique for accurate analog circuits macromodel sizing. - José Ángel Díaz-Madrid; Juan Hinojosa; Ginés Doménech-Asensi (Int. J. Circuit Theory Appl., 2010)

Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels. - Ginés Doménech-Asensi; José Ángel Díaz-Madrid; Ramón Ruiz Merino (Int. J. Circuit Theory Appl., 2013)

An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation. - José Ángel Díaz-Madrid; Ginés Doménech-Asensi; José-Alejandro López Alcantud; M. Oberst (ISCAS, 2017)

An all-hardware implementation of the subpixel refinement stage in SIFT algorithm. - Pablo Rubio-Ibáñez; Ramón Ruiz Merino; Ginés Doménech-Asensi; J. Javier Martínez-Álvarez; Juan Zapata-Pérez; José Ángel Díaz-Madrid; José-Alejandro López Alcantud (Int. J. Circuit Theory Appl., 2018)

Mixed Signal Multiply and Adder Parallel Circuit for Deep Learning Convolution Operations. - José Ángel Díaz-Madrid; Ginés Doménech-Asensi; Ramón Ruiz Merino; Juan Zapata-Pérez; José Javier Martínez 001 (ISCAS, 2020)

All-hardware SIFT implementation for real-time VGA images feature extraction. - Ginés Doménech-Asensi; Juan Zapata-Pérez; Ramón Ruiz Merino; José-Alejandro López Alcantud; José Ángel Díaz-Madrid; Víctor Manuel Brea Sánchez; Paula López 001 (J. Real Time Image Process., 2020)

Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC. - José Ángel Díaz-Madrid; Ginés Doménech-Asensi; J. Javier Martínez-Álvarez; Juan Zapata-Pérez; Ramón Ruiz Merino (Circuits Syst. Signal Process., 2021)

A 12T SRAM in-Memory Computing differential current architecture for CNN implementations. - Ginés Doménech-Asensi; Ramón Ruiz Merino; Juan Zapata-Pérez; José Ángel Díaz-Madrid (ISCAS, 2023)

A real-time and energy-efficient SRAM with mixed-signal in-memory computing near CMOS sensors. - José Ángel Díaz-Madrid; Ginés Doménech-Asensi; Ramón Ruiz Merino; Juan Zapata-Pérez (J. Real Time Image Process., 2024)

Interlaced 6T-10T CMOS in-memory computing circuit for low silicon area pipelined DNNs. - Ginés Doménech-Asensi; Francisco Javier Andreo-Oliver; Ramón Ruiz Merino; José Ángel Díaz-Madrid (ISCAS, 2025)