Low-distortion delta-sigma topologies for MASH architectures. - José B. Silva; Un-Ku Moon; Gabor C. Temes (ISCAS (1), 2004)

A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications. - Shelly Xiao; José B. Silva; Un-Ku Moon; Gabor C. Temes (ISCAS (1), 2004)

Theory and applications of incremental ΔΣ converters. - János Márkus; José B. Silva; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

A low-power 22-bit incremental ADC with 4 ppm INL, 2 ppm gain error and 2 μV DC offset. - Vincent Quiquempoix; Philippe Deval; Alexandre Barreto; Gabriele Bellini; Jerry Collings; János Márkus; José B. Silva; Gabor C. Temes (ESSCIRC, 2005)

Design-oriented estimation of thermal noise in switched-capacitor circuits. - Richard Schreier; José B. Silva; Jesper Steensgaard; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Incremental Delta-Sigma Structures for DC Measurement: an Overview. - János Márkus; Philippe Deval; Vincent Quiquempoix; José B. Silva; Gabor C. Temes (CICC, 2006)

A low-power 22-bit incremental ADC. - Vincent Quiquempoix; Philippe Deval; Alexandre Barreto; Gabriele Bellini; János Márkus; José B. Silva; Gabor C. Temes (IEEE J. Solid State Circuits, 2006)

15.5 A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS. - Yunzhi Dong; Jialin Zhao 001; Wenhua Yang 002; Trevor C. Caldwell; Hajime Shibata; Richard Schreier; Qingdong Meng; José B. Silva; Donald Paterson; Jeffrey C. Gealow (ISSCC, 2016)

A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS. - Yunzhi Dong; Jialin Zhao 001; Wenhua Yang 002; Trevor C. Caldwell; Hajime Shibata; Zhao Li; Richard Schreier; Qingdong Meng; José B. Silva; Donald Paterson; Jeffrey C. Gealow (IEEE J. Solid State Circuits, 2016)

Adaptive digital noise-cancellation filtering using cross-correlators for continuous-time MASH ADC in 28nm CMOS. - Yunzhi Dong; José B. Silva; Qingdong Meng; Jialin Zhao 001; Wenhua Yang 002; Trevor C. Caldwell; Hajime Shibata; Zhao Li; Donald Paterson; Jeffrey C. Gealow (CICC, 2017)

16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology. - Siddharth Devarajan; Larry Singer; Dan Kelly; Steve Kosic; Tao Pan; José B. Silva; Janet Brunsilius; Daniel Rey-Losada; Frank Murden; Carroll Speir; Jeff Bray; Eric Otte; et al. (ISSCC, 2017)

A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology. - Siddharth Devarajan; Larry Singer; Dan Kelly; Tao Pan; José B. Silva; Janet Brunsilius; Daniel Rey-Losada; Frank Murden; Carroll Speir; Jeff Bray; Eric Otte; Nevena Rakuljic; et al. (IEEE J. Solid State Circuits, 2017)

A -89-dBc IMD3 DAC Sub-System in a 465-MHz BW CT Delta-Sigma ADC Using a Power and Area Efficient Calibration Technique. - Jialin Zhao 001; Yunzhi Dong; Wenhua Yang 002; Hajime Shibata; Prawal Shrestha; Zhao Li; Trevor C. Caldwell; José B. Silva; Jeffrey C. Gealow (IEEE Trans. Circuits Syst. II Express Briefs, 2018)