A frequency-domain approach to interconnect crosstalk simulation and minimization. - José Ernesto Rayas-Sánchez (Microelectron. Reliab., 2004)

Systematic configuration of coarsely discretized 3D EM solvers for reliable and fast simulation of high-frequency planar structures. - José Ernesto Rayas-Sánchez; Zabdiel Brito-Brito; Juan C. Cervantes-González; Carlos A. Lopez (LASCAS, 2013)

A digital predistortion technique based on a NARX network to linearize GaN class F power amplifiers. - Lina M. Aguilar-Lobo; Alberto Garcia-Osorio; José Raúl Loo-Yau; Susana Ortega-Cisneros; Pablo Moreno; José Ernesto Rayas-Sánchez; J. Apolinar Reynoso-Hernández (MWSCAS, 2014)

Impedance matching analysis and EMC validation of a low-cost PCB differential interconnect. - J. Rafael del-Rey; Zabdiel Brito-Brito; José Ernesto Rayas-Sánchez (LATS, 2015)

Design of experiments implementation towards optimization of power distribution networks. - Felipe de Jesus Leal-Romo; José Ernesto Rayas-Sánchez; Jiangqi He (LASCAS, 2017)

Analysis of the implications of stacked devices in nano-scale technologies for analog applications. - Ismael Lomeli-Illescas; Sergio A. Solis-Bustos; José Ernesto Rayas-Sánchez (LATS, 2017)

Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation. - Francisco E. Rangel-Patino; José Ernesto Rayas-Sánchez; Nagib Hakim (ITC, 2018)

Jitter tolerance acceleration using the golden section optimization technique. - Andres Viveros-Wacher; Ricardo Baca-Baylon; Francisco E. Rangel-Patino; Miguel A. Davalos-Santana; Edgar-Andrei Vega-Ochoa; José Ernesto Rayas-Sánchez (LASCAS, 2018)

Direct optimization of a PCI express link equalization in industrial post-silicon validation. - Francisco E. Rangel-Patino; José Ernesto Rayas-Sánchez; Edgar-Andrei Vega-Ochoa; Nagib Hakim (LATS, 2018)

A tool for the automatic generation and analysis of regular analog layout modules. - Ismael Lomeli-Illescas; Sergio A. Solis-Bustos; José Ernesto Rayas-Sánchez (Integr., 2019)

Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks. - Francisco E. Rangel-Patino; José Ernesto Rayas-Sánchez; Andres Viveros-Wacher; José Luis Chavez-Hurtado; Edgar-Andrei Vega-Ochoa; Nagib Hakim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Machine Learning Techniques and Space Mapping Approaches to Enhance Signal and Power Integrity in High-Speed Links and Power Delivery Networks. - José Ernesto Rayas-Sánchez; Francisco E. Rangel-Patino; Benjamin Mercado-Casillas; Felipe de Jesus Leal-Romo; José Luis Chávez-Hurtado (LASCAS, 2020)

A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation. - Francisco E. Rangel-Patino; Andres Viveros-Wacher; José Ernesto Rayas-Sánchez; Ismael Duron-Rosales; Edgar-Andrei Vega-Ochoa; Nagib Hakim; Enrique Lopez-Miralrio (IEEE Trans. Emerg. Top. Comput., 2020)

Frequency- and Time-Domain Yield Optimization of a Power Delivery Network Subject to Large Decoupling Capacitor Tolerances. - Aurea Edna Moreno-Mojica; José Ernesto Rayas-Sánchez (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)