An Interface Based on Transputers to Simulate the Dynamic Equation of Robot Manipulators Using Parallel Computing. - Juan Carlos Fernández 002; Lourdes Peñalver; M. Sobejano; José F. Martínez; Vicente Hernández; Josep Tornero (VECPAR, 1996)

DAMISYS: An Overview. - M. Covadonga Fernández; Oscar Delgado; J. Ignacio López; M. Angeles Luna; José F. Martínez; J. F. Borja Pardo; José M. Peña 002 (DaWaK, 1999)

Improving the performance of bristled CC-NUMA systems using virtual channels and adaptivity. - José F. Martínez; Josep Torrellas; José Duato (International Conference on Supercomputing, 1999)

Architectural support for scalable speculative parallelization in shared-memory multiprocessors. - Marcelo H. Cintra; José F. Martínez; Josep Torrellas (ISCA, 2000)

Speculative synchronization: applying thread-level speculation to explicitly parallel applications. - José F. Martínez; Josep Torrellas (ASPLOS, 2002)

Cherry: checkpointed early resource recycling in out-of-order microprocessors. - José F. Martínez; Jose Renau; Michael C. Huang 001; Milos Prvulovic; Josep Torrellas (MICRO, 2002)

Speculative Shared -Memory Architectures - José F. Martínez (2002)

A Case for Resource-conscious Out-of-order Processors. - Adrián Cristal; José F. Martínez; Josep Llosa; Mateo Valero (IEEE Comput. Archit. Lett., 2003)

Speculative Synchronization: Programmability and Performance for Parallel Codes. - José F. Martínez; Josep Torrellas (IEEE Micro, 2003)

The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors. - Jian Li 059; José F. Martínez; Michael C. Huang 001 (HPCA, 2004)

Feature Selection Using Typical Testors Applied to Estimation of Stellar Parameters. - José A. Santos; Ariel Carrasco; José F. Martínez (Computación y Sistemas, 2004)

A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. - Adrián Cristal; José F. Martínez; Josep Llosa; Mateo Valero (SIGARCH Comput. Archit. News, 2004)

Toward kilo-instruction processors. - Adrián Cristal; Oliverio J. Santana; Mateo Valero; José F. Martínez (ACM Trans. Archit. Code Optim., 2004)

Checkpointed Early Load Retirement. - Nevin Kirman; Meyrem Kirman; Mainak Chaudhuri; José F. Martínez (HPCA, 2005)

Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors. - Jian Li 059; José F. Martínez (ISPASS, 2005)

Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors. - Meyrem Kirman; Nevin Kirman; José F. Martínez (MICRO, 2005)

Power-performance considerations of parallel computing on chip multiprocessors. - Jian Li 059; José F. Martínez (ACM Trans. Archit. Code Optim., 2005)

Dynamic power-performance adaptation of parallel computation on chip multiprocessors. - Jian Li 059; José F. Martínez (HPCA, 2006)

Dynamic program phase detection in distributed shared-memory multiprocessors. - Engin Ipek; José F. Martínez; Bronis R. de Supinski; Sally A. McKee; Martin Schulz 001 (IPDPS, 2006)

Leveraging Optical Technology in Future Bus-based Chip Multiprocessors. - Nevin Kirman; Meyrem Kirman; Rajeev K. Dokania; José F. Martínez; Alyssa B. Apsel; Matthew A. Watkins; David H. Albonesi (MICRO, 2006)

Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor. - Christopher LaFrieda; Engin Ipek; José F. Martínez; Rajit Manohar (DSN, 2007)

A Reconfigurable Chip Multiprocessor Architecture to Accommodate Software Diversity. - Engin Ipek; Meyrem Kirman; Nevin Kirman; José F. Martínez (IPDPS, 2007)

Core fusion: accommodating software diversity in chip multiprocessors. - Engin Ipek; Meyrem Kirman; Nevin Kirman; José F. Martínez (ISCA, 2007)

Scavenger: A New Last Level Cache Architecture with Global Block Priority. - Arkaprava Basu; Nevin Kirman; Meyrem Kirman; Mainak Chaudhuri; José F. Martínez (MICRO, 2007)

On-Chip Optical Technology in Future Bus-Based Multicore Designs. - Nevin Kirman; Meyrem Kirman; Rajeev K. Dokania; José F. Martínez; Alyssa B. Apsel; Matthew A. Watkins; David H. Albonesi (IEEE Micro, 2007)

Self-Optimizing Memory Controllers: A Reinforcement Learning Approach. - Engin Ipek; Onur Mutlu; José F. Martínez; Rich Caruana (ISCA, 2008)

Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach. - Ramazan Bitirgen; Engin Ipek; José F. Martínez (MICRO, 2008)

Dynamic Multicore Resource Management: A Machine Learning Approach. - José F. Martínez; Engin Ipek (IEEE Micro, 2009)

A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing. - Nevin Kirman; José F. Martínez (ASPLOS, 2010)

The DiY Smart Experiences Project - A European Endeavour Removing Barriers for User-generated Internet of Things Applications. - Marc Roelands; Johan Plomp; Diego Casado Mansilla; Juan R. Velasco; Ismail Salhi; Gyu Myoung Lee; Noël Crespi; Filipe Vinci dos Santos; Julien Vachaudez; Frédéric Bettens; Joel Hanqc; Carlos Valderrama; et al. (Architecting the Internet of Things, 2011)

MORSE: Multi-objective reconfigurable self-optimizing memory scheduler. - Janani Mukundan; José F. Martínez (HPCA, 2012)

Overcoming single-thread performance hurdles in the core fusion reconfigurable multicore architecture. - Janani Mukundan; Saugata Ghose; Robert Karmazin; Engin Ipek; José F. Martínez (ICS, 2012)

Building service-oriented Smart Infrastructures over Wireless Ad Hoc Sensor Networks: A middleware perspective. - Miguel S. Familiar; José F. Martínez; Iván Corredor; Carlos García-Rubio (Comput. Networks, 2012)

Knowledge-Aware and Service-Oriented Middleware for deploying pervasive services. - Iván Corredor; José F. Martínez; Miguel S. Familiar; Lourdes López-Santidrián (J. Netw. Comput. Appl., 2012)

Improving memory scheduling via processor-side load criticality information. - Saugata Ghose; Hyodong Lee; José F. Martínez (ISCA, 2013)

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems. - Janani Mukundan; Hillery C. Hunter; Kyu-Hyoun Kim; Jeffrey Stuecheli; José F. Martínez (ISCA, 2013)

A Message from the New Editor-in-Chief and Introduction of New Associate Editors. - José F. Martínez (IEEE Comput. Archit. Lett., 2013)

Editorial. - José F. Martínez (IEEE Comput. Archit. Lett., 2013)

GraphGen: An FPGA Framework for Vertex-Centric Graph Computation. - Eriko Nurvitadhi; Gabriel Weisz; Yu Wang 110; Skand Hurkat; Marie Nguyen; James C. Hoe; José F. Martínez; Carlos Guestrin (FCCM, 2014)

A hardware architecture for filtering irreducible testors. - Vladimir Rodriguez; José F. Martínez; Jesús Ariel Carrasco-Ochoa; Manuel Sabino Lazo-Cortés; René Cumplido; Claudia Feregrino Uribe (ReConFig, 2014)

Service architecting and dynamic composition in pervasive smart ecosystems for the internet of things based on sensor network technology. - Miguel S. Familiar; José F. Martínez; Carlos García-Rubio (J. Ambient Intell. Smart Environ., 2014)

Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference. - Skand Hurkat; Jungwook Choi; Eriko Nurvitadhi; José F. Martínez; Rob A. Rutenbar (FPL, 2015)

XChange: A market-based approach to scalable dynamic multi-resource allocation in multicore architectures. - Xiaodong Wang; José F. Martínez (HPCA, 2015)

ReBudget: Trading Off Efficiency vs. Fairness in Market-Based Multicore Resource Allocation via Runtime Budget Reassignment. - Xiaodong Wang; José F. Martínez (ASPLOS, 2016)

SWAP: Effective Fine-Grain Management of Shared Last-Level Caches with Minimum Hardware Support. - Xiaodong Wang; Shuang Chen 002; Jeff Setter; José F. Martínez (HPCA, 2017)

Workload characterization of interactive cloud services on big and small server platforms. - Shuang Chen 002; Shay GalOn; Christina Delimitrou; Srilatha Manne; José F. Martínez (IISWC, 2017)

PARTIES: QoS-Aware Resource Partitioning for Multiple Interactive Services. - Shuang Chen 002; Christina Delimitrou; José F. Martínez (ASPLOS, 2019)

VIP: A Versatile Inference Processor. - Skand Hurkat; José F. Martínez (HPCA, 2019)

VisSched: An Auction-Based Scheduler for Vision Workloads on Heterogeneous Processors. - Diksha Moolchandani; Anshul Kumar; José F. Martínez; Smruti R. Sarangi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

CAPE: A Content-Addressable Processing Engine. - Helena Caminal; Kailin Yang; Srivatsa Srinivasa; Akshay Krishna Ramanathan; Khalid Al-Hawaj; Tianshu Wu; Vijaykrishnan Narayanan; Christopher Batten; José F. Martínez (HPCA, 2021)

ReTail: Opting for Learning Simplicity to Enable QoS-Aware Power Management in the Cloud. - Shuang Chen 002; Angela Jin; Christina Delimitrou; José F. Martínez (HPCA, 2022)

PIMCloud: QoS-Aware Resource Management of Latency-Critical Applications in Clouds with Processing-in-Memory. - Shuang Chen 002; Yi Jiang; Christina Delimitrou; José F. Martínez (HPCA, 2022)

Accelerating database analytic query workloads using an associative processor. - Helena Caminal; Yannis Chronis; Tianshu Wu; Jignesh M. Patel; José F. Martínez (ISCA, 2022)

PUMICE: Processing-using-Memory Integration with a Scalar Pipeline for Symbiotic Execution. - Socrates S. Wong; Cecilio C. Tamarit; José F. Martínez (DAC, 2023)

Comosum: An Extensible, Reconfigurable, and Fault-Tolerant IoT Platform for Digital Agriculture. - Gloire Rubambiza; Shiang-Wan Chin; Mueed Rehman; Sachille Atapattu; José F. Martínez; Hakim Weatherspoon (USENIX ATC, 2023)

Constraints on Research in Biological and Agricultural Science in Developing Countries: The Example of Latin America. - Carlos S. Galina; José F. Martínez; Bruce D. Murphy (Publ., 2023)

FloatAP: Supporting High-Performance Floating-Point Arithmetic in Associative Processors. - Kailin Yang; José F. Martínez (MICRO, 2024)

DReX: Accurate and Scalable Dense Retrieval Acceleration via Algorithmic-Hardware Codesign. - Derrick Quinn; E. Ezgi Yücel; Martin Prammer; Zhenxing Fan; Kevin Skadron; Jignesh M. Patel; José F. Martínez; Mohammad Alian (ISCA, 2025)

Membrane: Accelerating Database Analytics with Bank-Level DRAM-PIM Filtering. - Akhil Shekar; Kevin P. Gaffney; Martin Prammer; Khyati Kiyawat; Lingxi Wu; Helena Caminal; Zhenxing Fan; Yimin Gao; Ashish Venkat; José F. Martínez; Jignesh M. Patel; Kevin Skadron (CoRR, 2025)

VersaTile: Flexible Tiled Architectures via Associative Processors. - Kailin Yang; José F. Martínez (ACM Trans. Archit. Code Optim., 2025)