BVE: a wafer-scale engine for differential equation computation. - José G. Delgado-Frias; D. M. Green (ICS, 1988)

Parallel architectures for AI semantic network processing. - José G. Delgado-Frias; Will R. Moore (Knowl. Based Syst., 1988)

A semantic network architecture for artificial intelligence processing. - José G. Delgado-Frias; Will R. Moore (TAI, 1989)

MPU: A N-Tuple Matching Processor. - Robert H. Payne; José G. Delgado-Frias (ICCD, 1991)

AI in multimedia (panel session). - Nikolaos G. Bourbakis; Robin Williams 001; Forouzan Golshani; Myron Flickner; Ted Laliotis; Sukhan Lee 001; José G. Delgado-Frias; Dan Hammerstrom; Cris Koutsougeras; Gerald G. Pechanek; Benjamin W. Wah; John Yen; et al. (ICTAI, 1991)

SPIN: a sequential pipelined neurocomputer. - Stamatis Vassiliadis; Gerald G. Pechanek; José G. Delgado-Frias (ICTAI, 1991)

Semantic Network Architectures: an Evaluation. - José G. Delgado-Frias; Stamatis Vassiliadis; Jamshid Goshtasbi (Int. J. Artif. Intell. Tools, 1992)

Digital neural emulators using tree accumulation and communication structures. - Gerald G. Pechanek; Stamatis Vassiliadis; José G. Delgado-Frias (IEEE Trans. Neural Networks, 1992)

A massively parallel diagonal-fold array processor. - Gerald G. Pechanek; José G. Delgado-Frias; Stamatis Vassiliadis (ASAP, 1993)

Spin: the Sequential Pipelined Neuroemulator. - Stamatis Vassiliadis; Gerald G. Pechanek; José G. Delgado-Frias (Int. J. Artif. Intell. Tools, 1993)

A VLSI CAM-based flexible oblivious router for multiprocessor interconnection networks. - José G. Delgado-Frias; Rovy Sze; Douglas H. Summerville; Valentine C. Aikens II (Great Lakes Symposium on VLSI, 1994)

A High Performance Pattern Associative Oblivious Router for Tree Topologies. - Douglas H. Summerville; José G. Delgado-Frias; Stamatis Vassiliadis (IPPS, 1994)

Design and evaluation of a DAMQ multiprocessor network with self-compacting buffers. - Joonho Park; Brian W. O'Krafka; Stamatis Vassiliadis; José G. Delgado-Frias (SC, 1994)

An investigation of binary CLA and ripple CMOS adder designs. - Chuan-Jen Chang; Stamatis Vassiliadis; José G. Delgado-Frias (Microprocess. Microprogramming, 1994)

A Neuro-Architecture with Embedded Learning. - Valentine C. Aikens II; Steven M. Barber; José G. Delgado-Frias; Gerald G. Pechanek; Stamatis Vassiliadis (Parallel and Distributed Computing and Systems, 1995)

A VLSI-Processing and Communicating Pipelined Tree for Parallel Computing. - Adger E. Harvin III; José G. Delgado-Frias (Parallel and Distributed Computing and Systems, 1995)

A Pattern-Associative Router for Adaptive Algorithms in Hypercube Networks. - Daniel G. Rice; José G. Delgado-Frias; Douglas H. Summerville (Parallel and Distributed Computing and Systems, 1995)

Flexible oblivious router architecture. - Joonho Park; Stamatis Vassiliadis; José G. Delgado-Frias (IBM J. Res. Dev., 1995)

The multi-associative branch target buffer: a cost effective BTB mechanism. - Weili Chu; Stamatis Vassiliadis; José G. Delgado-Frias (Microprocess. Microprogramming, 1995)

A Pattern-Associative Router for Interconnection Network Adaptive Algorithms. - Daniel G. Rice; José G. Delgado-Frias; Douglas H. Summerville (Euro-Par, Vol. I, 1996)

A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh. - José G. Delgado-Frias; Jabulani Nyathi; Chester L. Miller; Douglas H. Summerville (Great Lakes Symposium on VLSI, 1996)

A neuro-emulator with learning and virtual emulation capabilities. - Valentine C. Aikens II; José G. Delgado-Frias; Steven M. Barber; Gerald G. Pechanek; Stamatis Vassiliadis (ICNN, 1996)

Software Metrics and Microcode: A Case Study. - George Triantafyllos; Stamatis Vassiliadis; José G. Delgado-Frias (J. Softw. Maintenance Res. Pract., 1996)

Sigmoid Generators for Neural Computing Using Piecewise Approximations. - Ming Zhang; Stamatis Vassiliadis; José G. Delgado-Frias (IEEE Trans. Computers, 1996)

A Flexible Bit-Pattern Associative Router for Interconnection Networks. - Douglas H. Summerville; José G. Delgado-Frias; Stamatis Vassiliadis (IEEE Trans. Parallel Distributed Syst., 1996)

Approaches for determining dynamic synchronization resource requirements. - Douglas H. Summerville; José G. Delgado-Frias (CATA, 1998)

A VLSI Self-Compacting Buffer for DAMQ Communication Switches. - José G. Delgado-Frias; Richard Diaz (Great Lakes Symposium on VLSI, 1998)

A VLSI High-Performance Encoder with Priority Lookahead. - José G. Delgado-Frias; Jabulani Nyathi (Great Lakes Symposium on VLSI, 1998)

A Dictionary Machine Emulation on a VLSI Computing Tree System. - Adger E. Harvin III; José G. Delgado-Frias (Great Lakes Symposium on VLSI, 1998)

A Clustering and Genetic Scheme for Large Tsp Optimization Problems. - Chien-Ying Lu; José G. Delgado-Frias; Wei Lin (Cybern. Syst., 1998)

Executing tree routing algorithms on a high-performance pattern associative router. - Douglas H. Summerville; José G. Delgado-Frias; Stamatis Vassiliadis (J. Syst. Archit., 1998)

A neuro-emulator with embedded capabilities for generalized learning. - Valentine C. Aikens II; José G. Delgado-Frias; Gerald G. Pechanek; Stamatis Vassiliadis (J. Syst. Archit., 1999)

A wave-pipelined router architecture using ternary associative memory. - José G. Delgado-Frias; Jabulani Nyathi; Laxmi N. Bhuyan (ACM Great Lakes Symposium on VLSI, 2000)

A wave-pipelined CMOS associate router for communication switches. - José G. Delgado-Frias; Jabulani Nyathi (ISCAS, 2000)

Elementary function generators for neural-network emulators. - Stamatis Vassiliadis; Ming Zhang; José G. Delgado-Frias (IEEE Trans. Neural Networks Learn. Syst., 2000)

A VLSI wrapped wave front arbiter for crossbar switches. - José G. Delgado-Frias; Girish B. Ratanpal (ACM Great Lakes Symposium on VLSI, 2001)

BASIS: A Biological Approach to System Information Security. - Victor A. Skormin; José G. Delgado-Frias; Dennis L. McGee; Joseph Giordano; Leonard J. Popyack; Vladimir I. Gorodetski; Alexander O. Tarakanov (MMM-ACNS, 2001)

A Reconfigurable Switch for a DSP Array. - Fred L. Anderson IV; José G. Delgado-Frias (VLSI, 2003)

A Fault-Tolerant Memory-Based Cell for a Reconfigurable DSP Processor. - Daniel R. Blum; José G. Delgado-Frias (VLSI, 2003)

A Two-Level Reconfigurable Architecture for Digital Signal Processing. - Mitchell J. Myjak; José G. Delgado-Frias (VLSI, 2003)

A Distributed FIFO Scheme for System on Chip Inter-Component Communication. - Ray Robert Rydberg III; Jabulani Nyathi; José G. Delgado-Frias (ESA/VLSI, 2004)

An H-Tree Based Configuration Scheme for Reconfigurable DSP Hardware. - Andy Widjaja; José G. Delgado-Frias (ESA/VLSI, 2004)

H-Tree Interconnection Structure for Reconfigurable DSP Hardware. - Mitchell J. Myjak; Fredrick L. Anderson; José G. Delgado-Frias (ERSA, 2004)

Pipelined Multipliers for Reconfigurable Hardware. - Mitchell J. Myjak; José G. Delgado-Frias (IPDPS, 2004)

Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS. - Daniel R. Blum; Mitchell J. Myjak; José G. Delgado-Frias (CDES, 2005)

DAMQ Self-Compacting Buffer Schemes for Systems with Network-On-Chip. - Jin Liu; José G. Delgado-Frias (CDES, 2005)

A Symmetric Differential Clock Generator for Bit-Serial Hardware. - Mitchell J. Myjak; José G. Delgado-Frias (CDES, 2005)

A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme. - Suryanarayana Tatapudi; José G. Delgado-Frias (CDES, 2005)

A distributed FIFO scheme for on chip communication. - Ray Robert Rydberg III; Jabulani Nyathi; José G. Delgado-Frias (ISCAS (2), 2005)

A High Performance Hybrid Wave-Pipelined Multiplier. - Suryanarayana Tatapudi; José G. Delgado-Frias (ISVLSI, 2005)

Decoupled dynamic ternary content addressable memories. - José G. Delgado-Frias; Jabulani Nyathi; Suryanarayana Tatapudi (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Mapping and Performance of DSP Benchmarks on a Medium-Grain Reconfigurable Architecture. - Mitchell J. Myjak; Jonathan Larson; José G. Delgado-Frias (ERSA, 2006)

Interleaved Multistage Switching Fabrics for Scalable High Performance Routers. - Rongsen He; José G. Delgado-Frias (GLOBECOM, 2006)

Superpipelined reconfigurable hardware for DSP. - Mitchell J. Myjak; José G. Delgado-Frias (ISCAS, 2006)

A mesochronous pipeline scheme for high performance low power digital systems. - Suryanarayana Tatapudi; José G. Delgado-Frias (ISCAS, 2006)

Performance Analysis of Multipath Data Transmission in Multihop Ad Hoc Networks. - Li Zhao; José G. Delgado-Frias (SECON, 2006)

Multipath Routing Based Secure Data Transmission in Ad Hoc Networks. - Li Zhao; José G. Delgado-Frias (WiMob, 2006)

On Throughput of Multipath Data Transmission over Multihop Ad Hoc Networks. - Li Zhao; José G. Delgado-Frias (Wireless and Optical Communications, 2006)

A mesochronous pipelining scheme for high-performance digital systems. - Suryanarayana Tatapudi; José G. Delgado-Frias (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

A novel compaction scheme for routing tables in TCAM to enhance cache hit rate. - R. Guo; José G. Delgado-Frias (Communications, Internet, and Information Technology, 2007)

Using a cache scheme to detect selfish nodes in mobile ad hoc networks. - H. Lin; José G. Delgado-Frias; Sirisha Medidi (Communications, Internet, and Information Technology, 2007)

Using a two-timer scheme to detect selfish nodes in mobile ad-hoc networks. - H. Lui; José G. Delgado-Frias; Sirisha Medidi (Communications, Internet, and Information Technology, 2007)

Redundant Array of Independent Fabrics - An Architecture for Next Generation Network. - Rongsen He; José G. Delgado-Frias (GLOBECOM, 2007)

MARS: Misbehavior Detection in Ad Hoc Networks. - Li Zhao; José G. Delgado-Frias (GLOBECOM, 2007)

Using a Cache Scheme to Detect Misbehaving Nodes in Mobile Ad-Hoc Networks. - Hongxun Liu; José G. Delgado-Frias; Sirisha Medidi (ICON, 2007)

Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories. - Daniel R. Blum; José G. Delgado-Frias (ISCAS, 2007)

Emergent societies: advanced IT support of crisis relief missions. - Peter Sapaty; Masanori Sugisaka; Robert Finkelstein; José G. Delgado-Frias; Nikolay N. Mirenkov (Artif. Life Robotics, 2007)

Preface. - Laurence Tianruo Yang; José G. Delgado-Frias; Yiming Li; Mohammed Y. Niamat; Dimitrios Soudris; Srinivasa Vemuru (Integr., 2007)

Medium-Grain Cells for Reconfigurable DSP Hardware. - Mitchell J. Myjak; José G. Delgado-Frias (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Fault Tolerant Interleaved Switching Fabrics For Scalable High-Performance Routers. - Rongsen He; José G. Delgado-Frias (IEEE Trans. Parallel Distributed Syst., 2007)

FPGA Schemes with Optimized Routing for the Advanced Encryption Standard. - Jason Van Dyken; José G. Delgado-Frias; Sirisha Medidi (ERSA, 2008)

High-performance low-power AND and Sense-Amp address decoders with selective precharging. - Michael A. Turi; José G. Delgado-Frias (ISCAS, 2008)

Intelligent management of distributed dynamic sensor networks. - Peter Sapaty; Masanori Sugisaka; José G. Delgado-Frias; Joaquim Filipe; Nikolay N. Mirenkov (Artif. Life Robotics, 2008)

Performance analysis of multipath transmission over 802.11-based multihop ad hoc networks: a cross-layer perspective. - Li Zhao; José G. Delgado-Frias; Krishnamoorthy Sivakumar (IET Commun., 2008)

High-Performance Low-Power Selective Precharge Schemes for Address Decoders. - Michael A. Turi; José G. Delgado-Frias (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance. - Mitchell J. Myjak; José G. Delgado-Frias (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures. - Kylan Robinson; José G. Delgado-Frias (ERSA, 2009)

IP Routing table compaction and sampling schemes to enhance TCAM cache performance. - Ruirui Guo; José G. Delgado-Frias (J. Syst. Archit., 2009)

Decreasing energy consumption in address decoders by means of selective precharge schemes. - Michael A. Turi; José G. Delgado-Frias (Microelectron. J., 2009)

Low power SRAM cell design for FinFET and CNTFET technologies. - José G. Delgado-Frias; Zhe Zhang; Michael A. Turi (Green Computing Conference, 2010)

FPGA Implementation of Adjustable Wideband Fractional Delay FIR Filters. - G. Ramirez-Conejo; Javier Díaz-Carmona; Agustín Ramírez-Agundis; Alfredo Padilla-Medina; José G. Delgado-Frias (ReConFig, 2010)

FPGA schemes for minimizing the power-throughput trade-off in executing the Advanced Encryption Standard algorithm. - Jason Van Dyken; José G. Delgado-Frias (J. Syst. Archit., 2010)

SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cells. - Zhe Zhang; Michael A. Turi; José G. Delgado-Frias (ACM Great Lakes Symposium on VLSI, 2012)

A superscalar processor for a medium-grain reconfigurable hardware. - Jason Van Dyken; José G. Delgado-Frias (MWSCAS, 2012)

FinFET 3T and 3T1D dynamic RAM cells. - Colby M. Gerik; Michael A. Turi; José G. Delgado-Frias (MWSCAS, 2012)

CNTFET SRAM cell with tolerance to removed metallic CNTs. - Zhe Zhang; José G. Delgado-Frias (MWSCAS, 2012)

NOA: A Scalable Multi-Parent Clustering Hierarchy for WSNs. - Johnathan Vee Cree; José G. Delgado-Frias; Mike Hughes; Brion Burghard; Kurt Silvers (ANT/MobiWIS, 2012)

Management of large-scale wireless sensor networks utilizing multi-parent recursive area hierarchies. - Johnathan Vee Cree; José G. Delgado-Frias (IGCC, 2013)

CNTFET 8T SRAM cell performance with near-threshold power supply scaling. - Zhe Zhang; José G. Delgado-Frias (ISCAS, 2013)

Near-threshold CNTFET SRAM cell design with gated cell power supply. - Zhe Zhang; José G. Delgado-Frias (MWSCAS, 2013)

Welcome to MWSCAS 2014. - José Silva-Martínez; Edgar Sánchez-Sinencio; José G. Delgado-Frias; Randall L. Geiger (MWSCAS, 2014)

An evaluation of 6T and 8T FinFET SRAM cell leakage currents. - Michael A. Turi; José G. Delgado-Frias (MWSCAS, 2014)

Near-threshold CNTFET SRAM cell design with removed metallic CNT tolerance. - José G. Delgado-Frias; Zhe Zhang; Michael A. Turi (ISCAS, 2015)

UEFI USB bus initialization verification using Colored Petri Net. - Rongyang Liu; José G. Delgado-Frias; Doug Boyce; Rahul Khanna (MWSCAS, 2015)

A real-time UEFI functional validation tool with behavior Colored Petri Net model. - Rongyang Liu; José G. Delgado-Frias; Doug Boyce; Rahul Khanna (MWSCAS, 2016)

Autonomous management of a recursive area hierarchy for large scale wireless sensor networks using multiple parents. - Johnathan Vee Cree; José G. Delgado-Frias (Ad Hoc Networks, 2016)

An implemented, initialization algorithm for many-dimension, Monte Carlo circuit simulations using Spice. - Michael A. Turi; José G. Delgado-Frias (CCWC, 2017)

Firmware functional validation using a Colored Petri Net model. - Rongyang Liu; José G. Delgado-Frias; Doug Boyce; Rahul Khanna (MWSCAS, 2017)

Full-VDD and near-threshold performance of 8T FinFET SRAM cells. - Michael A. Turi; José G. Delgado-Frias (Integr., 2017)

Online Firmware Functional Validation Scheme Using Colored Petri Net Model. - Rongyang Liu; José G. Delgado-Frias; Doug Boyce; Yi Qian 003; Rahul Khanna (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

MWSCAS Guest Editorial Special Issue Based on the 62nd International Midwest Symposium on Circuits and Systems. - José Silva-Martínez; José G. Delgado-Frias (IEEE Trans. Circuits Syst., 2020)

Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating. - Michael A. Turi; José G. Delgado-Frias (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Crosstalk-Harnessed Signaling Enhancement that Eliminates Common-Mode Encoding. - Daniel Iparraguirre; José G. Delgado-Frias; Howard Heck (ISCAS, 2021)

ACHS Optimizations on 3D Interconnect Arrangements. - Daniel Iparraguirre; José G. Delgado-Frias (ISCAS, 2022)

Asymmetric Crosstalk Harness Signaling for Common Eigenmode Elimination. - Daniel Iparraguirre; José G. Delgado-Frias; Howard Heck (IEEE Trans. Computers, 2022)

Asymmetric Crosstalk Harnessed Signaling for Large 3D Routing Integration. - Daniel Iparraguirre; José G. Delgado-Frias (IEEE Trans. Circuits Syst. II Express Briefs, 2022)