José González
Affiliations:- Intel Labs, Intel Barcelona Research Center, Spain
- University of Murcia, Spain (former)
- Technical University of Valencia, Spain (former)
According to our database1,
José González
authored at least 57 papers
between 1997 and 2013.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2013
Thread Row Buffers: Improving Memory Performance Isolation and Throughput in Multiprogrammed Environments.
IEEE Trans. Computers, 2013
2012
Distributed Cooperative Caching: An Energy Efficient Memory Scheme for Chip Multiprocessors.
IEEE Trans. Parallel Distributed Syst., 2012
2011
Trans. High Perform. Embed. Archit. Compil., 2011
Thread shuffling: combining DVFS and thread migration toreduce energy consumptions for multi-core systems.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
2010
Thread-management techniques to maximize efficiency in multicore and simultaneous multithreaded microprocessors.
ACM Trans. Archit. Code Optim., 2010
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010
2009
J. Syst. Softw., 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008
Meeting points: using thread criticality to adapt multicore hardware to parallel regions.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008
2007
IEEE Trans. Parallel Distributed Syst., 2007
An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology.
Parallel Comput., 2007
Proceedings of the 2007 workshop on MEmory performance, 2007
2006
Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
2005
Reducing 3D Fast Wavelet Transform Execution Time Using Blocking and the Streaming SIMD Extensions.
J. VLSI Signal Process., 2005
IEEE Trans. Parallel Distributed Syst., 2005
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005
2004
An Architecture for High-Performance Scalable Shared-Memory Multiprocessors Exploiting On-Chip Integration.
IEEE Trans. Parallel Distributed Syst., 2004
Parallel Comput., 2004
Proceedings of the 3rd Workshop on Memory Performance Issues, 2004
Proceedings of the 18th Annual International Conference on Supercomputing, 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
2003
Proceedings of the Parallel Processing and Applied Mathematics, 2003
Automatic Optimisation of Parallel Linear Algebra Routines in Systems with Variable Load.
Proceedings of the 11th Euromicro Workshop on Parallel, 2003
Proceedings of the 11th Euromicro Workshop on Parallel, 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003
2002
Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture.
Proceedings of the 2002 ACM/IEEE conference on Supercomputing, 2002
Proceedings of the 10th Euromicro Workshop on Parallel, 2002
Reducing the Latency of L2 Misses in Shared-Memory Multiprocessors through On-Chip Directory Integration.
Proceedings of the 10th Euromicro Workshop on Parallel, 2002
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002
Proceedings of the 16th international conference on Supercomputing, 2002
Proceedings of the 28th EUROMICRO Conference 2002, 4-6 September 2002, Dortmund, Germany, 2002
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002
2001
Proceedings of the Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001
Selective Branch Prediction Reversal By Correlating with Data Values and Control Flow.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001
Proceedings of the High Performance Computing - HiPC 2001, 8th International Conference, 2001
2000
J. Instr. Level Parallelism, 2000
1999
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999
Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, 1999
1998
Proceedings of the Vector and Parallel Processing, 1998
Proceedings of the 12th international conference on Supercomputing, 1998
Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31, 1998
1997
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997
Proceedings of the 11th international conference on Supercomputing, 1997
Proceedings of the Fourth International on High-Performance Computing, 1997
Proceedings of the Euro-Par '97 Parallel Processing, 1997