Memory Address Prediction for Data Speculation. - José González 002; Antonio González 001 (Euro-Par, 1997)

Virtual registers. - Antonio González 001; Mateo Valero; José González 002; Teresa Monreal Arnal (HiPC, 1997)

Speculative Execution via Address Prediction and Data Prefetching. - José González 002; Antonio González 001 (International Conference on Supercomputing, 1997)

The Design and Performance of a Conflict-Avoiding Cache. - Nigel P. Topham; Antonio González 001; José González 002 (MICRO, 1997)

Virtual-Physical Registers. - Antonio González 001; José González 002; Mateo Valero (HPCA, 1998)

The Potential of Data Value Speculation to Boost ILP. - José González 002; Antonio González 001 (International Conference on Supercomputing, 1998)

Limits of Instruction Level Parallelism with Data Value Speculation. - José González 002; Antonio González 001 (VECPAR, 1998)

Data value speculation in superscalar processors. - José González 002; Antonio González 001 (Microprocess. Microsystems, 1998)

Control-Flow Speculation through Value Prediction for Superscalar Processors. - José González 002; Antonio González 001 (IEEE PACT, 1999)

Delaying Physical Register Allocation through Virtual-Physical Registers. - Teresa Monreal; Antonio González 001; Mateo Valero; José González 002; Víctor Viñals (MICRO, 1999)

Dynamic Register Renaming Through Virtual-Physical Registers. - Teresa Monreal; Antonio González 001; Mateo Valero; José González 002; Víctor Viñals (J. Instr. Level Parallelism, 2000)

Confidence Estimation for Branch Prediction Reversal. - Juan L. Aragón; José González 002; José M. García 001; Antonio González 001 (HiPC, 2001)

A New Scalable Directory Architecture for Large-Scale Multiprocessors. - Manuel E. Acacio; José González 002; José M. García 001; José Duato (HPCA, 2001)

Selective Branch Prediction Reversal By Correlating with Data Values and Control Flow. - Juan L. Aragón; José González 002; José M. García 001; Antonio González 001 (ICCD, 2001)

Modeling the Behaviour of Linear Algebra Algorithms with Message-Passing. - Javier Cuenca 001; Domingo Giménez; José González 002 (PDP, 2001)

Control-Flow Speculation through Value Prediction. - José González 002; Antonio González 001 (IEEE Trans. Computers, 2001)

The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors. - Manuel E. Acacio; José González 002; José M. García 001; José Duato (IEEE PACT, 2002)

Memory Conscious 3D Wavelet Transform. - Gregorio Bernabé; José González 002; José M. García 001; José Duato (EUROMICRO, 2002)

Dual path instruction processing. - Juan L. Aragón; José González 002; Antonio González 001; James E. Smith 001 (ICS, 2002)

A Novel Approach to Reduce L2 Miss Latency in Shared-Memory Multiprocessors. - Manuel E. Acacio; José González 002; José M. García 001; José Duato (IPDPS, 2002)

Reducing the Latency of L2 Misses in Shared-Memory Multiprocessors through On-Chip Directory Integration. - Manuel E. Acacio; José González 002; José M. García 001; José Duato (PDP, 2002)

Towards the Design of an Automatically Tuned Linear Algebra Library. - Javier Cuenca 001; Domingo Giménez; José González 002 (PDP, 2002)

Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture. - Manuel E. Acacio; José González 002; José M. García 001; José Duato (SC, 2002)

Power-Aware Control Speculation through Selective Throttling. - Juan L. Aragón; José González 002; Antonio González 001 (HPCA, 2003)

Dynamic Cluster Resizing. - José González 002; Antonio González 001 (ICCD, 2003)

Reducing 3D Wavelet Transform Execution Time through the Streaming SIMD Extensions. - Gregorio Bernabé; José M. García 001; José González 002 (PDP, 2003)

Automatic Optimisation of Parallel Linear Algebra Routines in Systems with Variable Load. - Javier Cuenca 001; Domingo Giménez; José González 002; Jack J. Dongarra; Kenneth Roche (PDP, 2003)

Empirical Modelling of Parallel Linear Algebra Routines. - Javier Cuenca 001; Luis-Pedro García; Domingo Giménez; José González 002; Antonio M. Vidal (PPAM, 2003)

Thermal-Aware Clustered Microarchitectures. - Pedro Chaparro; José González 002; Antonio González 001 (ICCD, 2004)

Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2. - Grigorios Magklis; José González 002; Antonio González 001 (ICCD, 2004)

Back-end assignment schemes for clustered multithreaded processors. - Fernando Latorre; José González 002; Antonio González 001 (ICS, 2004)

Cache organizations for clustered microarchitectures. - José González 002; Fernando Latorre; Antonio González 001 (WMPI, 2004)

Architecture of an automatically tuned linear algebra library. - Javier Cuenca 001; Domingo Giménez; José González 002 (Parallel Comput., 2004)

Late Allocation and Early Release of Physical Registers. - Teresa Monreal; Víctor Viñals; José González 002; Antonio González 001; Mateo Valero (IEEE Trans. Computers, 2004)

An Architecture for High-Performance Scalable Shared-Memory Multiprocessors Exploiting On-Chip Integration. - Manuel E. Acacio; José González 002; José M. García 001; José Duato (IEEE Trans. Parallel Distributed Syst., 2004)

Distributing the Frontend for Temperature Reduction. - Pedro Chaparro; Grigorios Magklis; José González 002; Antonio González 001 (HPCA, 2005)

A Two-Level Directory Architecture for Highly Scalable cc-NUMA Multiprocessors. - Manuel E. Acacio; José González 002; José M. García 001; José Duato (IEEE Trans. Parallel Distributed Syst., 2005)

Reducing 3D Fast Wavelet Transform Execution Time Using Blocking and the Streaming SIMD Extensions. - Gregorio Bernabé; José M. García 001; José González 002 (J. VLSI Signal Process., 2005)

Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture. - Grigorios Magklis; Pedro Chaparro; José González 002; Antonio González 001 (ISLPED, 2006)

Building a large instruction window through ROB compression. - Fernando Latorre; Grigorios Magklis; José González 002; Pedro Chaparro; Antonio González 001 (MEDEA@PACT, 2007)

An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology. - Gregorio Bernabé; Ricardo Fernández-Pascual; José M. García 001; Manuel E. Acacio; José González 002 (Parallel Comput., 2007)

Understanding the Thermal Implications of Multi-Core Architectures. - Pedro Chaparro; José González 002; Grigorios Magklis; Qiong Cai; Antonio González 001 (IEEE Trans. Parallel Distributed Syst., 2007)

Meeting points: using thread criticality to adapt multicore hardware to parallel regions. - Qiong Cai; José González 002; Ryan N. Rakvic; Grigorios Magklis; Pedro Chaparro; Antonio González 001 (PACT, 2008)

Distributed cooperative caching. - Enric Herrero; José González 002; Ramon Canal (PACT, 2008)

A software-hardware hybrid steering mechanism for clustered microarchitectures. - Qiong Cai; Josep M. Codina; José González 002; Antonio González 001 (IPDPS, 2008)

Efficient resources assignment schemes for clustered multithreaded processors. - Fernando Latorre; José González 002; Antonio González 001 (IPDPS, 2008)

Thread fusion. - José González 002; Qiong Cai; Pedro Chaparro; Grigorios Magklis; Ryan N. Rakvic; Antonio González 001 (ISLPED, 2008)

Dynamic thermal management using thin-film thermoelectric cooling. - Pedro Chaparro; José González 002; Qiong Cai; Greg Chrysler (ISLPED, 2009)

A lossy 3D wavelet transform for high-quality compression of medical video. - Gregorio Bernabé; José M. García 001; José González 002 (J. Syst. Softw., 2009)

Power-Efficient Spilling Techniques for Chip Multiprocessors. - Enric Herrero; José González 002; Ramon Canal (Euro-Par (1), 2010)

Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors. - Enric Herrero; José González 002; Ramon Canal (ISCA, 2010)

Energy efficiency via thread fusion and value reuse. - Ryan N. Rakvic; José González 002; Qiong Cai; Pedro Chaparro; Grigorios Magklis; Antonio González 001 (IET Comput. Digit. Tech., 2010)

Thread-management techniques to maximize efficiency in multicore and simultaneous multithreaded microprocessors. - Ryan N. Rakvic; Qiong Cai; José González 002; Grigorios Magklis; Pedro Chaparro; Antonio González 001 (ACM Trans. Archit. Code Optim., 2010)

Thread shuffling: combining DVFS and thread migration toreduce energy consumptions for multi-core systems. - Qiong Cai; José González 002; Grigorios Magklis; Pedro Chaparro; Antonio González 001 (ISLPED, 2011)

CROB: Implementing a Large Instruction Window through Compression. - Fernando Latorre; Grigorios Magklis; José González 002; Pedro Chaparro; Antonio González 001 (Trans. High Perform. Embed. Archit. Compil., 2011)

Distributed Cooperative Caching: An Energy Efficient Memory Scheme for Chip Multiprocessors. - Enric Herrero; José González 002; Ramon Canal (IEEE Trans. Parallel Distributed Syst., 2012)

Thread Row Buffers: Improving Memory Performance Isolation and Throughput in Multiprogrammed Environments. - Enric Herrero; José González 002; Ramon Canal; Dean M. Tullsen (IEEE Trans. Computers, 2013)