José A. Joao

Orcid: 0000-0002-3571-5562

According to our database1, José A. Joao authored at least 22 papers between 2006 and 2023.

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Bibliography

2023
DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2020
In-Hardware Moving Compute to Data Model to Accelerate Thread Synchronization on Large Multicores.
IEEE Micro, 2020

2019
DynaSprint: Microarchitectural Sprints with Dynamic Utility and Thermal Management.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

On the Benefits of Tasking with OpenMP.
Proceedings of the OpenMP: Conquering the Full Hardware Spectrum, 2019

Cache Line Sharing and Communication in ECP Proxy Applications.
Proceedings of the OpenMP: Conquering the Full Hardware Spectrum, 2019

2018
Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Accelerating Synchronization in Graph Analytics Using Moving Compute to Data Model on Tilera TILE-Gx72.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

BUQS: Battery- and user-aware QoS scaling for interactive mobile devices.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
ARM HPC Ecosystem and the Reemergence of Vectors: Invited Paper.
Proceedings of the Computing Frontiers Conference, 2017

2013
Utility-based acceleration of multithreaded applications on asymmetric CMPs.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2012
Bottleneck identification and scheduling in multithreaded applications.
Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012

2011
Data Marshaling for Multicore Systems.
IEEE Micro, 2011

Parallel application memory scheduling.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

2010
Data marshaling for multi-core architectures.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

2009
Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware.
IEEE Trans. Computers, 2009

Flexible reference-counting-based hardware acceleration for garbage collection.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

2008
Dynamic Predication of Indirect Jumps.
IEEE Comput. Archit. Lett., 2008

Improving the performance of object-oriented languages with dynamic predication of indirect jumps.
Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008

2007
Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication.
IEEE Micro, 2007

VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors.
Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007

2006
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006


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