Gbit/second lossless data compression hardware. - José Luis Núñez-Yáñez (2001)

A code compression scheme for improving SoC performance. - E. G. Nikolova; David J. Mulvaney; Vassilios A. Chouliaras; José L. Núñez-Yáñez (SoC, 2003)

Scalar coprocessors for accelerating the G723.1 and G729A speech coders. - Vassilios A. Chouliaras; José L. Núñez-Yáñez (IEEE Trans. Consumer Electron., 2003)

A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor. - Tom R. Jacobs; José L. Núñez-Yáñez (ASAP, 2005)

Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec. - José L. Núñez-Yáñez; Vassilios A. Chouliaras (ASAP, 2005)

Configurable Multiprocessors for High-Performance MPEG-4 Video Coding. - Vassilios A. Chouliaras; Tom R. Jacobs; Ashwin K. Kumaraswamy; José L. Núñez-Yáñez (ISVLSI, 2005)

Applying data-parallel and scalar optimizations for the efficient implementation of the G.729A and G.723.1 speech coding standards. - Konstantia Koutsomyti; S. R. Parr; Vassilios A. Chouliaras; José L. Núñez-Yáñez (SIP, 2005)

A Configurable Statistical Lossless Compression Core Based on Variable Order Markov Modeling and Arithmetic Coding. - José L. Núñez-Yáñez; Vassilios A. Chouliaras (IEEE Trans. Computers, 2005)

A multi-standard video accelerator based on a vector architecture. - Vassilios A. Chouliaras; José L. Núñez-Yáñez; David J. Mulvaney; Fabrizio S. Rovati; Daniele Alfonso (IEEE Trans. Consumer Electron., 2005)

High-performance arithmetic coding VLSI macro for the H264 video compression standard. - José L. Núñez-Yáñez; Vassilios A. Chouliaras (IEEE Trans. Consumer Electron., 2005)

A Novel Processor Architecture for Real-Time Control. - Xiaofeng Wu 001; Vassilios A. Chouliaras; José L. Núñez-Yáñez; Roger Goodall; Tanya Vladimirova (Asia-Pacific Computer Systems Architecture Conference, 2006)

Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec. - José L. Núñez-Yáñez; Vassilios A. Chouliaras; Daniele Alfonso; Fabrizio S. Rovati (IEEE Trans. Consumer Electron., 2006)

Dynamic Voltage Scaling in a FPGA-based System-on-Chip. - José L. Núñez-Yáñez; Vassilios A. Chouliaras; Jiri Gaisler (FPL, 2007)

On the Hardware Reduction of z-Datapath of Vectoring CORDIC. - R. Stapenhurst; Koushik Maharatna; Jimson Mathew; José L. Núñez-Yáñez; Dhiraj K. Pradhan (ISCAS, 2007)

Hardware architecture for lossless image compression based on context-based modeling and arithmetic coding. - Xiaolin Chen; Nishan Canagarajah; José Luis Núñez-Yáñez; Raffaele Vitulli (SoCC, 2007)

Statistical Lossless Compression of Space Imagery and General Data in a Reconfigurable Architecture. - José Luis Núñez-Yáñez; Xiaolin Chen; Nishan Canagarajah; Raffaele Vitulli (AHS, 2008)

Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture. - Xiaolin Chen; Cedric Nishan Canagarajah; Raffaele Vitulli; José L. Núñez-Yáñez (ARC, 2008)

Fault-tolerant dynamically reconfigurable NoC-based SoC. - Mohammad Hosseinabady; José L. Núñez-Yáñez (ASAP, 2008)

Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration. - Izhar Zaidi; Atukem Nabina; Cedric Nishan Canagarajah; José L. Núñez-Yáñez (DSD, 2008)

A configurable and programmable motion estimation processor for the H.264 video codec. - José Luis Núñez-Yáñez; Eddie Hung; Vassilios A. Chouliaras (FPL, 2008)

Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor. - Izhar Zaidi; Atukem Nabina; Cedric Nishan Canagarajah; José L. Núñez-Yáñez (FPL, 2008)

Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems. - José L. Núñez-Yáñez; Doug A. Edwards; Antonio Marcello Coppola (IET Comput. Digit. Tech., 2008)

Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study. - Vassilios A. Chouliaras; Vincent M. Dwyer; Shahrukh Agha; José L. Núñez-Yáñez; Dionysios I. Reisis; Konstantinos Nakos; Konstantinos Manolopoulos (Integr., 2008)

A Novel Delta Sigma Control System Processor and Its VLSI Implementation. - Xiaofeng Wu 001; Vassilios A. Chouliaras; José L. Núñez-Yáñez; Roger M. Goodall (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Energy optimization in a Network-on-Chip with dynamically reconfigurable processing nodes. - José L. Núñez-Yáñez; Mohammad Hosseinabady; Atukem Nabina; Izhar Zaidi (CCA/ISIC, 2009)

Run-time resource management in fault-tolerant network on reconfigurable chips. - Mohammad Hosseinabady; José L. Núñez-Yáñez (FPL, 2009)

A toolset for the analysis and optimization of motion estimation algorithms and processors. - Trevor Spiteri; George Vafiadis; José Luis Núñez-Yáñez (FPL, 2009)

A biophysically accurate floating point somatic neuroprocessor. - Yiwei Zhang 002; José L. Núñez-Yáñez; Joe McGeehan; Edward Regan; Stephen Kelly (FPL, 2009)

Adaptive stochastic routing in fault-tolerant on-chip networks. - Wei Song 002; Doug A. Edwards; José Luis Núñez-Yáñez; Sohini Dasgupta (NOCS, 2009)

Backward Adaptive Pixel-based Fast Predictive Motion Estimation. - Xiaolin Chen; Nishan Canagarajah; José L. Núñez-Yáñez (IEEE Signal Process. Lett., 2009)

SystemC Architectural Transaction Level Modelling for Large NoCs. - Mohammad Hosseinabady; José L. Núñez-Yáñez (FDL, 2010)

Dynamic Reconfiguration Optimisation with Streaming Data Decompression. - Atukem Nabina; José L. Núñez-Yáñez (FPL, 2010)

Effective modelling of large NoCs using SystemC. - Mohammad Hosseinabady; José L. Núñez-Yáñez (ISCAS, 2010)

Task Dispersal Measurement in Dynamic Reconfigurable NoCs. - Mohammad Hosseinabady; José Luis Núñez-Yáñez; Antonio Marcello Coppola (ISVLSI, 2010)

Multi-standard reconfigurable motion estimation processor for hybrid video codecs. - José L. Núñez-Yáñez; Trevor Spiteri; George Vafiadis (IET Comput. Digit. Tech., 2011)

Approximate alpha-stable Markov Random Fields for video super-resolution. - Jin Chen; José L. Núñez-Yáñez; Alin Achim (EUSIPCO, 2012)

Exploring dynamically reconfigurable multicore designs with NoRC designer. - José L. Núñez-Yáñez; Arash Beldachi; Atukem Nabina; Mohammad Hosseinabady (HPCS, 2012)

Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles. - Mohammad Hosseinabady; José Luis Núñez-Yáñez (IET Comput. Digit. Tech., 2012)

Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation. - Mohammad Hosseinabady; José Luis Núñez-Yáñez (IET Comput. Digit. Tech., 2012)

Lossless video compression based on backward adaptive pixel-based fast motion estimation. - Xiaolin Chen; Nishan Canagarajah; José Luis Núñez-Yáñez; Raffaele Vitulli (Signal Process. Image Commun., 2012)

Video Super-Resolution Using Generalized Gaussian Markov Random Fields. - Jin Chen; José L. Núñez-Yáñez; Alin Achim (IEEE Signal Process. Lett., 2012)

Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform. - Atukem Nabina; José Luis Núñez-Yáñez (ACM Trans. Reconfigurable Technol. Syst., 2012)

Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding. - José Luis Núñez-Yáñez; Atukem Nabina; Eddie Hung; George Vafiadis (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Energy proportional computing in commercial FPGAs with adaptive voltage scaling. - José L. Núñez-Yáñez (FPGAworld, 2013)

Video super-resolution using low rank matrix completion. - Jin Chen; José L. Núñez-Yáñez; Alin Achim (ICIP, 2013)

Numerically efficient and biophysically accurate neuroprocessing platform. - Juan Carlos Moctezuma; Joseph McGeehan; José Luis Núñez-Yáñez (ReConFig, 2013)

Enabling accurate modeling of power and energy consumption in an ARM-based System-on-Chip. - José L. Núñez-Yáñez; Geza Lore (Microprocess. Microsystems, 2013)

Biophysically Accurate Foating Point Neuroprocessors for Reconfigurable Logic. - Yiwei Zhang 002; Joseph McGeehan; Edward Regan; Stephen Kelly; José Luis Núñez-Yáñez (IEEE Trans. Computers, 2013)

Run-time power and performance scaling with CPU-FPGA hybrids. - José L. Núñez-Yáñez; Arash Beldachi (AHS, 2014)

Optimizing Memory Power in Hybrid ARM-FPGA Chips With Lossless Data Compression. - Peng Sun; José L. Núñez-Yáñez (FPGAworld, 2014)

Accurate power control and monitoring in ZYNQ boards. - Arash Farhadi Beldachi; José L. Núñez-Yáñez (FPL, 2014)

Run-time power gating in hybrid ARM-FPGA devices. - Mohammad Hosseinabady; José Luis Núñez-Yáñez (FPL, 2014)

Power modelling and capping for heterogeneous ARM/FPGA SoCs. - Yun Wu 003; José L. Núñez-Yáñez; Roger F. Woods; Dimitrios S. Nikolopoulos (FPT, 2014)

Joint video fusion and super resolution based on Markov random fields. - Jin Chen; José L. Núñez-Yáñez; Alin Achim (ICIP, 2014)

Neuron Dynamics of Two-compartment Traub Model for Hardware-based Emulation. - Juan Carlos Moctezuma; José Luis Núñez-Yáñez; Joseph P. McGeehan (IJCCI (NCTA), 2014)

eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip. - Arash Beldachi; Simon J. Hollis; José L. Núñez-Yáñez (IET Comput. Digit. Tech., 2014)

Run-time power and performance scaling in 28 nm FPGAs. - Arash Beldachi; José L. Núñez-Yáñez (IET Comput. Digit. Tech., 2014)

Energy efficient Reconfigurable Computing with Adaptive Voltage and Logic scaling. - José L. Núñez-Yáñez (SIGARCH Comput. Archit. News, 2014)

Bayesian Video Super-Resolution With Heavy-Tailed Prior Models. - Jin Chen; José Luis Núñez-Yáñez; Alin Achim (IEEE Trans. Circuits Syst. Video Technol., 2014)

Evaluation of Hybrid Run-Time Power Models for the ARM Big.LITTLE Architecture. - Krastin Nikov; José L. Núñez-Yáñez; Matthew Horsnell (EUC, 2015)

Energy optimization of FPGA-based stream-oriented computing with power gating. - Mohammad Hosseinabady; José Luis Núñez-Yáñez (FPL, 2015)

Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices. - Mohammad Hosseinabady; José Luis Núñez-Yáñez (FPL, 2015)

Workload distribution and balancing in FPGAs and CPUs with OpenCL and TBB. - Rafael Asenjo; Angeles G. Navarro; Andrés Rodríguez 001; José L. Núñez-Yáñez (PARCO, 2015)

Guest Editorial. - José L. Núñez-Yáñez; J. M. Moreno; Dimitrios S. Nikolopoulos (IET Comput. Digit. Tech., 2015)

Biologically compatible neural networks with reconfigurable hardware. - Juan Carlos Moctezuma; Joseph P. McGeehan; José Luis Núñez-Yáñez (Microprocess. Microsystems, 2015)

Adaptive Voltage Scaling with In-Situ Detectors in Commercial FPGAs. - José Luis Núñez-Yáñez (IEEE Trans. Computers, 2015)

Computing to the Limit with Heterogeneous CPU-FPGA Devices in a Video Fusion Application. - José L. Núñez-Yáñez (ARC, 2016)

Energy efficient video fusion with heterogeneous CPU-FPGA devices. - Peng Sun; Alin Achim; Ian Hasler; Paul R. Hill; José L. Núñez-Yáñez (DATE, 2016)

Energy proportional computing with OpenCL on a FPGA-based overlay architecture. - Awais Hussain Sani; José Luis Núñez-Yáñez (NORCAS, 2016)

CPCIe: A compression-enabled PCIe core for energy and performance optimization. - Mohd Amiruddin Zainol; José Luis Núñez-Yáñez (NORCAS, 2016)

Energy Efficient Video Fusion with Heterogeneous CPU-FPGA Devices. - José L. Núñez-Yáñez; Tom Sun (CoRR, 2016)

Editorial to special issue on energy efficient architectures for embedded systems. - Nuno Roma; José L. Núñez-Yáñez (EURASIP J. Embed. Syst., 2016)

Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling. - José Luis Núñez-Yáñez; Mohammad Hosseinabady; Arash Beldachi (IEEE Trans. Computers, 2016)

Optimal compression of vibration data with lifting wavelet transform and context-based arithmetic coding. - Yang Zhang 003; Paul Hutchinson; Nicholas A. J. Lieven; José L. Núñez-Yáñez (EUSIPCO, 2017)

A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis. - Mohammad Hosseinabady; José Luis Núñez-Yáñez (FPL, 2017)

Pipelined Streaming Computation of Histogram in FPGA OpenCL. - Mohammad Hosseinabady; José Luis Núñez-Yáñez (PARCO, 2017)

Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip. - José L. Núñez-Yáñez; Mohammad Hosseinabady; Andrés Rodríguez 001; Rafael Asenjo; Angeles G. Navarro; Ruben Gran Tejero; Darío Suárez Gracia (PARCO, 2017)

Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources. - Qianqiao Chen; Vaibhawa Mishra; José L. Núñez-Yáñez; Georgios Zervas (ReConFig, 2017)

Adaptive voltage scaling in a heterogeneous FPGA device with memory and logic in-situ detectors. - José L. Núñez-Yáñez (Microprocess. Microsystems, 2017)

Energy proportional streaming spiking neural network in a reconfigurable system. - Felipe Galindo Sanchez; José L. Núñez-Yáñez (Microprocess. Microsystems, 2017)

Multi-precision convolutional neural networks on heterogeneous hardware. - Sam Amiri; Mohammad Hosseinabady; Simon McIntosh-Smith; José L. Núñez-Yáñez (DATE, 2018)

Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips. - Sam Amiri; Mohammad Hosseinabady; Andrés Rodríguez 001; Rafael Asenjo; Angeles G. Navarro; José L. Núñez-Yáñez (FPL, 2018)

Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems. - José L. Núñez-Yáñez; Mohammad Hosseinabady; Moslem Amiri; Andrés Rodríguez 001; Rafael Asenjo; Angeles G. Navarro; Ruben Gran Tejero; Darío Suárez Gracia (CoRR, 2018)

Reconfigurable Network Stream Processing on Virtualized FPGA Resources. - Qianqiao Chen; Vaibhawa Mishra; José L. Núñez-Yáñez; Georgios Zervas (Int. J. Reconfigurable Comput., 2018)

Dynamic Energy Management of FPGA Accelerators in Embedded Systems. - Mohammad Hosseinabady; José Luis Núñez-Yáñez (ACM Trans. Embed. Comput. Syst., 2018)

Ultrasonic Levitation with Software-Defined FPGAs and Electronically Phased Arrays. - William Beasley; Brenda Gatusch; Daniel Connolly-Taylor; Chenyuan Teng; Asier Marzo; José L. Núñez-Yáñez (AHS, 2019)

Energy Proportional Heterogenous Computing with Reconfigurable MPSoC. - José L. Núñez-Yáñez (HPCS, 2019)

Relationship Estimation Metrics for Binary SoC Data. - Dave McEwan; José L. Núñez-Yáñez (LOD, 2019)

Visualizations for Understanding SoC Behaviour. - Dave McEwan; Marcin Hlond; José L. Núñez-Yáñez (PRIME, 2019)

Performance and Energy Efficiency Trade-Offs in Single-ISA Heterogeneous Multi-Processing for Parallel Applications. - Demetrios A. M. Coutinho; Kyriakos Georgiou; Kerstin I. Eder; José L. Núñez-Yáñez; Samuel Xavier de Souza (VLSI-SoC, 2019)

Heterogeneous FPGA+GPU Embedded Systems: Challenges and Opportunities. - Mohammad Hosseinabady; Mohd Amiruddin Bin Zainol; José L. Núñez-Yáñez (CoRR, 2019)

High-Performance Ultrasonic Levitation with FPGA-based Phased Arrays. - William Beasley; Brenda Gatusch; Daniel Connolly-Taylor; Chenyuan Teng; Asier Marzo; José L. Núñez-Yáñez (CoRR, 2019)

Relationship Detection Measures for Binary SoC Data. - Dave McEwan; José L. Núñez-Yáñez (CoRR, 2019)

Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs. - Andrés Rodríguez 001; Angeles G. Navarro; Rafael Asenjo; Francisco Corbera; Ruben Gran Tejero; Darío Suárez Gracia; José L. Núñez-Yáñez (J. Syst. Archit., 2019)

Energy Proportional Neural Network Inference with Adaptive Voltage and Frequency Scaling. - José L. Núñez-Yáñez (IEEE Trans. Computers, 2019)

Simultaneous multiprocessing in a software-defined heterogeneous FPGA. - José L. Núñez-Yáñez; Sam Amiri; Mohammad Hosseinabady; Andrés Rodríguez 001; Rafael Asenjo; Angeles G. Navarro; Darío Suárez Gracia; Ruben Gran (J. Supercomput., 2019)

Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA. - José L. Núñez-Yáñez; Sam Amiri; Mohammad Hosseinabady; Andrés Rodríguez 001; Rafael Asenjo; Angeles G. Navarro; Darío Suárez Gracia; Ruben Gran (J. Supercomput., 2019)

Sparse Matrix-Dense Matrix Multiplication on Heterogeneous CPU+FPGA Embedded System. - Mohammad Hosseinabady; José L. Núñez-Yáñez (PARMA-DITAM@HiPEAC, 2020)

Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling. - José L. Núñez-Yáñez; Kris Nikov; Kerstin Eder; Mohammad Hosseinabady (PARMA-DITAM@HiPEAC, 2020)

Remaining Useful Life Estimation Using Long Short-Term Memory Neural Networks and Deep Fusion. - Yang Zhang 003; Paul Hutchinson; Nicholas A. J. Lieven; José L. Núñez-Yáñez (IEEE Access, 2020)

Performance and Energy Trade-Offs for Parallel Applications on Heterogeneous Multi-Processing Systems. - Demetrios A. M. Coutinho; Daniele De Sensi; Arthur Francisco Lorenzon; Kyriakos Georgiou; José L. Núñez-Yáñez; Kerstin Eder; Samuel Xavier de Souza (CoRR, 2020)

High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip. - Kris Nikov; Mohammad Hosseinabady; Rafael Asenjo; Andrés Rodríguez 001; Angeles G. Navarro; José L. Núñez-Yáñez (CoRR, 2020)

Intra and inter-core power modelling for single-ISA heterogeneous processors. - Krastin Nikov; José L. Núñez-Yáñez (Int. J. Embed. Syst., 2020)

A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis. - Mohammad Hosseinabady; José Luis Núñez-Yáñez (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform. - Andrés Rodríguez 001; Angeles G. Navarro; Rafael Asenjo; Francisco Corbera; Ruben Gran; Darío Suárez Gracia; José L. Núñez-Yáñez (J. Supercomput., 2020)

Sparse and dense matrix multiplication hardware for heterogeneous multi-precision neural networks. - José L. Núñez-Yáñez; Mohammad Hosseinabady (Array, 2021)

Energy-efficient neural networks with near-threshold processors and hardware accelerators. - José L. Núñez-Yáñez; Neil J. Howard (J. Syst. Archit., 2021)

Entropy-Based Early-Exit in a FPGA-Based Low-Precision Neural Network. - Minxuan Kong; José Luis Núñez-Yáñez (ARC, 2022)

Evaluation of Early-exit Strategies in Low-cost FPGA-based Binarized Neural Networks. - Minxuan Kong; Kris Nikov; José Luis Núñez-Yáñez (DSD, 2022)

Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications. - Kaan Olgu; Kris Nikov; José L. Núñez-Yáñez (DSD, 2022)

A Low-complexity FPGA TDC based on a DSP Delay Line and a Wave Union Launcher. - Zijie Wang; Jiajun Lu; José L. Núñez-Yáñez (DSD, 2022)

Accurate Energy Modelling on the Cortex-M0 Processor for Profiling and Static Analysis. - Kris Nikov; Kyriakos Georgiou; Zbigniew Chamski; Kerstin Eder; José L. Núñez-Yáñez (ICECS 2022, 2022)

Robust and Accurate Fine-Grain Power Models for Embedded Systems With No On-Chip PMU. - Kris Nikov; Marcos Martínez; Simon Wegener; José L. Núñez-Yáñez; Zbigniew Chamski; Kyriakos Georgiou; Kerstin Eder (IEEE Embed. Syst. Lett., 2022)

Lightweight asynchronous scheduling in heterogeneous reconfigurable systems. - Andrés Rodríguez 001; Angeles G. Navarro; Kris Nikov; José L. Núñez-Yáñez; Ruben Gran; Darío Suárez Gracia; Rafael Asenjo (J. Syst. Archit., 2022)

Fused Architecture for Dense and Sparse Matrix Processing in TensorFlow Lite. - José L. Núñez-Yáñez (IEEE Micro, 2022)

GR712RC LEON3 Power Model Data. - Kris Nikov; Marcos Martínez; Pedro Vallejo; Abel Balbis; José L. Núñez-Yáñez; Kerstin Eder (IEEE DataPort, 2022)

Accelerating Graph Neural Networks in Pytorch with HLS and Deep Dataflows. - José L. Núñez-Yáñez (ARC, 2023)

Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning. - Andrés Otero; Guillermo Sanllorente; Eduardo de la Torre; José L. Núñez-Yáñez (ARC, 2023)

Multiple Human Tracking and Fall Detection Real-Time System Using Millimeter-Wave Radar and Data Fusion. - Zichao Shen; José L. Núñez-Yáñez; Naim Dahnoun (MECO, 2023)

EnergyAnalyzer: Using Static WCET Analysis Techniques to Estimate the Energy Consumption of Embedded Applications. - Simon Wegener; Kris K. Nikov; José L. Núñez-Yáñez; Kerstin Eder (WCET, 2023)

Big-Little Adaptive Neural Networks on Low-Power Near-Subthreshold Processors. - Zichao Shen; Neil J. Howard; José L. Núñez-Yáñez (CoRR, 2023)

Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite. - José L. Núñez-Yáñez; J. Andrés Otero; Eduardo de la Torre (Microprocess. Microsystems, 2023)

Deep Quantization of Graph Neural Networks with Run-Time Hardware-Aware Training. - Olle Hansson; Mahdieh Grailoo; Oscar Gustafsson; José L. Núñez-Yáñez (ARC, 2024)

Optimisation and Evaluation of Breadth First Search with oneAPI/SYCL on Intel FPGAs: from Describing Algorithms to Describing Architectures. - Kaan Olgu; Tobias Kenter; José L. Núñez-Yáñez; Simon McIntosh-Smith (IWOCL, 2024)

MMIDNet: Secure Human Identification Using Millimeter-wave Radar and Deep Learning. - Zichao Shen; José L. Núñez-Yáñez; Naim Dahnoun (MECO, 2024)

Hardware Acceleration of Molecular Property Graph Prediction on a Heterogeneous Edge Platform. - Mahdieh Grailoo; Tooraj Nikoubin; José L. Núñez-Yáñez (NorCAS, 2024)

Joint CPU-FPGA Hardware-Aware Quantized Training of Graph Convolutional Networks. - Olle Hansson; Oscar Gustafsson; José L. Núñez-Yáñez (NorCAS, 2024)

Leveraging Dynamic Range Analysis for Efficient Post-Training Quantization in Graph Convolutional Networks. - Hadi Mousanejad Jeddi; Mahdieh Grailoo; José L. Núñez-Yáñez (NorCAS, 2024)

Adaptive Quantization of Graph Convolutional Networks with Hardware-Aware On-device Training. - José L. Núñez-Yáñez (NorCAS, 2024)

Advanced Millimeter-Wave Radar System for Real-Time Multiple-Human Tracking and Fall Detection. - Zichao Shen; José L. Núñez-Yáñez; Naim Dahnoun (Sensors, 2024)

A Survey of Computationally Efficient Graph Neural Networks for Reconfigurable Systems. - Habib Taha Kose; José L. Núñez-Yáñez; Robert J. Piechocki; James Pope (Inf., 2024)