José L. Sánchez

Orcid: 0000-0002-3498-9174

Affiliations:
  • University of Castilla-La Mancha, Spain


According to our database1, José L. Sánchez authored at least 118 papers between 1995 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2023
Using graphics processing units for the efficient dynamic simulation of wind farms.
Comput. Electr. Eng., December, 2023

Extending the VEF traces framework to model data center network workloads.
J. Supercomput., 2023

Using GPUs to simulate photovoltaic power plants: Special cases of performance loss.
J. Comput. Sci., 2023

Energy efficient HPC network topologies with on/off links.
Future Gener. Comput. Syst., 2023

2022
Providing quality of service in omni-path networks.
J. Supercomput., 2022


2021
Enabling Quality of Service Provision in Omni-Path Switches.
Comput. Math. Methods, November, 2021

UPR: deadlock-free dynamic network reconfiguration by exploiting channel dependency graph compatibility.
J. Supercomput., 2021

A methodology to enable QoS provision on InfiniBand hardware.
J. Supercomput., 2021

DVL-Lossy: Isolating Congesting Flows to Optimize Packet Dropping in Lossy Data-Center Networks.
IEEE Micro, 2021

QoS provision in hierarchical and non-hierarchical switch architectures.
J. Parallel Distributed Comput., 2021

Supporting Efficient Assignment of Medical Resources in Cancer Treatments with Simulation-Optimization.
Proceedings of the Winter Simulation Conference, 2021

2020
TDSR: Transparent Distributed Segment-Based Routing.
CoRR, 2020

Optimizing Packet Dropping by Efficient Congesting-Flow Isolation in Lossy Data-Center Networks.
Proceedings of the IEEE Symposium on High-Performance Interconnects, 2020

2019
Optimization of lateral interaction in accumulative computation on GPU-based platform.
J. Supercomput., 2019

Accelerating bioinspired lateral interaction in accumulative computation for real-time moving object detection with graphics processing units.
Nat. Comput., 2019

Speeding up exascale interconnection network simulations with the VEF3 trace framework.
J. Parallel Distributed Comput., 2019

Energy efficient torus networks with on/off links.
J. Parallel Distributed Comput., 2019

Silicon photonic networks: Signal loss and power challenges.
Concurr. Comput. Pract. Exp., 2019

Constructing virtual 5-dimensional tori out of lower-dimensional network cards.
Concurr. Comput. Pract. Exp., 2019

Methodology for Decoupled Simulation of SystemVerilog HDL Designs.
Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019

2018
A Finite State Machine Approach to Algorithmic Lateral Inhibition for Real-Time Motion Detection.
Sensors, 2018

TopGen: A Library to Provide Simulation Tools with the Modeling of Interconnection Network Topologies.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

VEF3 Traces: Towards a Complete Framework for Modelling Network Workloads for Exascale Systems.
Proceedings of the 4th IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era, 2018

Analyzing Topology Parameters for Achieving Energy-Efficient k-ary n-cubes.
Proceedings of the 4th IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era, 2018

2017
An efficiency study of a pivot-based algorithm for similarity search on a heterogeneous platform.
J. Supercomput., 2017

GPU-based exhaustive algorithms processing kNN queries.
J. Supercomput., 2017

Applying search algorithms to obtain the optimal configuration of nDT torus nodes.
Concurr. Comput. Pract. Exp., 2017

Acceleration of Moving Object Detection in Bio-Inspired Computer Vision.
Proceedings of the Biomedical Applications Based on Natural and Artificial Computing, 2017

A Case Study on Implementing Virtual 5D Torus Networks Using Network Components of Lower Dimensionality.
Proceedings of the 3rd IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era, 2017

PhotoNoCs: Design Simulation Tool for Silicon Integrated Photonics Towards Exascale Systems.
Proceedings of the Euro-Par 2017: Parallel Processing Workshops, 2017

2016
An open-source family of tools to reproduce MPI-based workloads in interconnection network simulators.
J. Supercomput., 2016

Adaptive Routing for N-Dimensional Twin Torus.
IEEE Trans. Computers, 2016

2015
Optimizing the configuration of combined high-radix switches.
J. Supercomput., 2015

N-Dimensional Twin Torus Topology.
IEEE Trans. Computers, 2015

VEF Traces: A Framework for Modelling MPI Traffic in Interconnection Network Simulators.
Proceedings of the 2015 IEEE International Conference on Cluster Computing, 2015

2014
Formalization and configuration methodology for high-radix combined switches.
J. Supercomput., 2014

Towards an efficient static scheduling scheme for delivering queries to heterogeneous clusters in the similarity search problem.
J. Supercomput., 2014

Building 3D Torus Using Low-Profile Expansion Cards.
IEEE Trans. Computers, 2014

Optimal Configuration for N-Dimensional Twin Torus Networks.
Proceedings of the 2014 IEEE 13th International Symposium on Network Computing and Applications, 2014

Deadlock-free routing mechanism for 3D twin torus networks.
Proceedings of the 8th International Workshop on Interconnection Network Architecture, 2014

2013
An integrated solution for QoS provision and congestion management in high-performance interconnection networks using deterministic source-based routing.
J. Supercomput., 2013

H.264/AVC inter prediction for heterogeneous computing systems.
J. Supercomput., 2013

A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs.
ACM Trans. Embed. Comput. Syst., 2013

H.264/AVC inter prediction on accelerator-based multi-core systems.
Multim. Tools Appl., 2013

Obtaining the optimal configuration of high-radix Combined switches.
J. Parallel Distributed Comput., 2013

Adapting hierarchical bidirectional inter prediction on a GPU-based platform for 2D and 3D H.264 video coding.
EURASIP J. Adv. Signal Process., 2013

3D high definition video coding on a GPU-based heterogeneous system.
Comput. Electr. Eng., 2013

Low delay H.264/AVC bidirectional inter prediction on a GPU.
Proceedings of the IEEE International Conference on Image Processing, 2013

2012
Network-on-Chip virtualization in Chip-Multiprocessor Systems.
J. Syst. Archit., 2012

Hardware implementation study of several new egress link scheduling algorithms.
J. Parallel Distributed Comput., 2012

Optimizing H.264/AVC interprediction on a GPU-based framework.
Concurr. Comput. Pract. Exp., 2012

OSR-Lite: Fast and deadlock-free NoC reconfiguration framework.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Optimal Configuration of High-Radix Combined Switches.
Proceedings of the 20th Euromicro International Conference on Parallel, 2012

Exploring NoC Virtualization Alternatives in CMPs.
Proceedings of the 20th Euromicro International Conference on Parallel, 2012

A Fast GPU-Based Motion Estimation Algorithm for H.264/AVC.
Proceedings of the Advances in Multimedia Modeling - 18th International Conference, 2012

A Fast GPU-Based Motion Estimation Algorithm for HD 3D Video Coding.
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

Improving the Performance for the Range Search on Metric Spaces Using a Multi-GPU Platform.
Proceedings of the Database and Expert Systems Applications, 2012

2011
A GPU-based implementation of the MRF algorithm in ITK package.
J. Supercomput., 2011

Virtualizing network-on-chip resources in chip-multiprocessors.
Microprocess. Microsystems, 2011

Evaluation of an Alternative for Increasing Switch Radix.
Proceedings of The Tenth IEEE International Symposium on Networking Computing and Applications, 2011

NoC Reconfiguration for CMP Virtualization.
Proceedings of The Tenth IEEE International Symposium on Networking Computing and Applications, 2011

Reducing complexity in H.264/AVC motion estimation by using a GPU.
Proceedings of the IEEE 13th International Workshop on Multimedia Signal Processing (MMSP 2011), 2011

Self-related traces: An alternative to full-system simulation for NoCs.
Proceedings of the 2011 International Conference on High Performance Computing & Simulation, 2011

Similarity search implementations for multi-core and many-core processors.
Proceedings of the 2011 International Conference on High Performance Computing & Simulation, 2011

A GPU-Based Implementation for Range Queries on Spaghettis Data Structure.
Proceedings of the Computational Science and Its Applications - ICCSA 2011, 2011

C-Switches: Increasing Switch Radix with Current Integration Scale.
Proceedings of the 13th IEEE International Conference on High Performance Computing & Communication, 2011

A fast centralized computation routing algorithm for self-configuring NoC systems.
Proceedings of the 18th International Conference on High Performance Computing, 2011

2010
Providing QoS with the Deficit Table Scheduler.
IEEE Trans. Parallel Distributed Syst., 2010

A GPU-Based DVC to H.264/AVC Transcoder.
Proceedings of the Hybrid Artificial Intelligence Systems, 5th International Conference, 2010

2009
A Switch Architecture Guaranteeing QoS Provision and HOL Blocking Elimination.
IEEE Trans. Parallel Distributed Syst., 2009

A new strategy to manage the InfiniBand arbitration tables.
J. Parallel Distributed Comput., 2009

Hardware Implementation Study of the Deficit Table Egress Link Scheduling Algorithm.
Proceedings of the ICPP 2009, 2009

Hardware Implementation Study of the SCFQ-CA and DRR-CA Scheduling Algorithms.
Proceedings of the Euro-Par 2009 Parallel Processing, 2009

2008
A Framework to Provide Quality of Service over Advanced Switching.
IEEE Trans. Parallel Distributed Syst., 2008

Efficient Deadline-Based QoS Algorithms for High-Performance Networks.
IEEE Trans. Computers, 2008

2007
A New Cost-Effective Technique for QoS Support in Clusters.
IEEE Trans. Parallel Distributed Syst., 2007

A Formal Model to Manage the InfiniBand Arbitration Tables Providing QoS.
IEEE Trans. Computers, 2007

A low-cost strategy to provide full QoS support in Advanced Switching networks.
J. Syst. Archit., 2007

Efficient Switches with QoS Support for Clusters.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Deadline-based QoS Algorithms for High-performance Networks.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Comparing the latency performance of the DTable and DRR schedulers.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Providing Full QoS with 2 VCs in High-Speed Switches.
Proceedings of the Information Networking. Towards Ubiquitous Networking and Services, 2007

Integrated QoS Provision and Congestion Management for Interconnection Networks.
Proceedings of the Euro-Par 2007, 2007

2006
Full QoS Support with 2 VCs for Single-chip Switches.
Proceedings of the Fifth IEEE International Symposium on Network Computing and Applications, 2006

Implementing the Advanced Switching Minimum Bandwidth Egress Link Scheduler.
Proceedings of the Fifth IEEE International Symposium on Network Computing and Applications, 2006

Studying Several Proposals for the Adaptation of the DTable Scheduler to Advanced Switching.
Proceedings of the Parallel and Distributed Processing and Applications, 2006

Decoupling the Bandwidth and Latency Bounding for Table-based Schedulers.
Proceedings of the 2006 International Conference on Parallel Processing (ICPP 2006), 2006

Scalable Low-Cost QoS Support for Single-chip Switches.
Proceedings of the 12th International Conference on Parallel and Distributed Systems, 2006

Providing Quality of Service over Advanced Switching.
Proceedings of the 12th International Conference on Parallel and Distributed Systems, 2006

Evaluating several implementations for the AS Minimum Bandwidth Egress Link Scheduler.
Proceedings of the 15th International Conference On Computer Communications and Networks, 2006

QoS Support for Video Transmission in High-Speed Interconnects.
Proceedings of the High Performance Computing and Communications, 2006

Improving the Flexibility of the Deficit Table Scheduler.
Proceedings of the High Performance Computing, 2006

Towards a Cost-Effective Interconnection Network Architecture with QoS and Congestion Management Support.
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006

2005
Studying the Effect of the Design Parameters on the Interconnection Network Performance in NOWs.
Proceedings of the 13th Euromicro Workshop on Parallel, 2005

Studying the Influence of the InfiniBand Packet Size to Guarantee QoS.
Proceedings of the 10th IEEE Symposium on Computers and Communications (ISCC 2005), 2005

Providing Full QoS Support in Clusters Using Only Two VCs at the Switches.
Proceedings of the High Performance Computing, 2005

2004
QoS in InfiniBand Subnetworks.
IEEE Trans. Parallel Distributed Syst., 2004

An analysis of deadlock risk during centralized network mapping.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2004

A Methodology to Evaluate the Effectiveness of Traffic Balancing Algorithms.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

Tuning Buffer Size in InfiniBand to Guarantee QoS.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

2003
A New Proposal to Fill in the InfiniBand Arbitration Tables.
Proceedings of the 32nd International Conference on Parallel Processing (ICPP 2003), 2003

2002
Evaluation of Alternative Arbitration Policies for Myrinet Switches.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

A Strategy to Compute the InfiniBand Arbitration Tables.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

A Strategy to Manage Time Sensitive Traffic in InfiniBand.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

2001
A Protocol for Deadlock-Free Dynamic Reconfiguration in High-Speed Local Area Networks.
IEEE Trans. Parallel Distributed Syst., 2001

2000
Dynamic reconfiguration of node location in wormhole networks.
J. Syst. Archit., 2000

Performance Evaluation of Dynamic Reconfiguration in High-Speed Local Area Networks.
Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

Extending Dynamic Reconfiguration to NOWs with Adaptive Routing.
Proceedings of the Network-Based Parallel Computing: Communication, 2000

On the Performance of Up*/Down* Routing.
Proceedings of the Network-Based Parallel Computing: Communication, 2000

1999
An Efficient Load Balancing Method for Parallel Ray Tracing on Heterogeneous Workstation Networks.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

Deadlock-Free Routing in Irregular Networks with Dynamic Reconfiguration.
Proceedings of the Network-Based Parallel Computing: Communication, 1999

1998
Using channel pipelining in reconfigurable interconnection networks.
Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing, 1998

Reconfigurable Wormhole Networks: A Realistic Approach.
Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998

1997
A Function to Dynamic Workload Allocation in Distributed Applications.
Proceedings of the Recent Advances in Parallel Virtual Machine and Message Passing Interface, 1997

Interconnection network behavior on a multicomputer in the parallelization of the MPEG coding algorithm. Worm-hole vs. packet-switching routing.
Proceedings of the Fourth International on High-Performance Computing, 1997

1996
PEPE: A Trace-Driven Simulator to Evaluate Reconfigurable Multicomputer Architectures.
Proceedings of the Applied Parallel Computing, 1996

1995
Improving the Performance of Parallel Triangularization of a Sparse Matrix Using a Reconfigurable Multicomputer.
Proceedings of the Applied Parallel Computing, 1995


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