Improving the Performance of Parallel Triangularization of a Sparse Matrix Using a Reconfigurable Multicomputer. - José L. Sánchez 002; José M. García 001; Joaquin Fernández (PARA, 1995)

PEPE: A Trace-Driven Simulator to Evaluate Reconfigurable Multicomputer Architectures. - José M. García 001; José L. Sánchez 002; Pascual González (PARA, 1996)

Interconnection network behavior on a multicomputer in the parallelization of the MPEG coding algorithm. Worm-hole vs. packet-switching routing. - Teresa Olivares Montes; Pedro Angel Cuenca-Castillo; Francisco José Quiles Flor; Antonio Jose Garrido del Solo; José Luis Sánchez Garcia; José Duato Marín (HiPC, 1997)

A Function to Dynamic Workload Allocation in Distributed Applications. - Francisco José Alfaro; José A. Gallud; José L. Sánchez 002 (PVM/MPI, 1997)

Reconfigurable Wormhole Networks: A Realistic Approach. - José L. Sánchez 002; José M. García 001; Francisco José Alfaro (IPPS/SPDP Workshops, 1998)

Using channel pipelining in reconfigurable interconnection networks. - José L. Sánchez 002; José Duato; José M. García 001 (PDP, 1998)

Deadlock-Free Routing in Irregular Networks with Dynamic Reconfiguration. - Rafael Casado; Francisco J. Quiles 001; José L. Sánchez 002; José Duato (CANPC, 1999)

An Efficient Load Balancing Method for Parallel Ray Tracing on Heterogeneous Workstation Networks. - Pascual González; José L. Sánchez 002; Francisco José Alfaro (PDPTA, 1999)

On the Performance of Up*/Down* Routing. - Francisco José Alfaro; Aurelio Bermúdez; Rafael Casado; José Duato; Francisco J. Quiles 001; José L. Sánchez 002 (CANPC, 2000)

Extending Dynamic Reconfiguration to NOWs with Adaptive Routing. - Aurelio Bermúdez; Francisco José Alfaro; Rafael Casado; José Duato; Francisco J. Quiles 001; José L. Sánchez 002 (CANPC, 2000)

Performance Evaluation of Dynamic Reconfiguration in High-Speed Local Area Networks. - Rafael Casado; Aurelio Bermúdez; Francisco J. Quiles 001; José L. Sánchez 002; José Duato (HPCA, 2000)

Dynamic reconfiguration of node location in wormhole networks. - José L. Sánchez 002; José M. García 001 (J. Syst. Archit., 2000)

A Protocol for Deadlock-Free Dynamic Reconfiguration in High-Speed Local Area Networks. - Rafael Casado; Aurelio Bermúdez; José Duato; Francisco J. Quiles 001; José L. Sánchez 002 (IEEE Trans. Parallel Distributed Syst., 2001)

A Strategy to Manage Time Sensitive Traffic in InfiniBand. - Francisco José Alfaro; José L. Sánchez 002; José Duato (IPDPS, 2002)

A Strategy to Compute the InfiniBand Arbitration Tables. - Francisco José Alfaro; José L. Sánchez 002; José Duato; Chita R. Das (IPDPS, 2002)

Evaluation of Alternative Arbitration Policies for Myrinet Switches. - Pedro Javier García; M. D. Mora; Francisco José Alfaro; José L. Sánchez 002; José Flich (IPDPS, 2002)

A New Proposal to Fill in the InfiniBand Arbitration Tables. - Francisco José Alfaro; José L. Sánchez 002; José Duato (ICPP, 2003)

Tuning Buffer Size in InfiniBand to Guarantee QoS. - Francisco José Alfaro; José L. Sánchez 002 (Euro-Par, 2004)

A Methodology to Evaluate the Effectiveness of Traffic Balancing Algorithms. - J. E. Villalobos; José L. Sánchez 002; José A. Gámez 001; José Carlos Sancho; Antonio Robles (Euro-Par, 2004)

An analysis of deadlock risk during centralized network mapping. - Pedro Javier García; Francisco J. Quiles 001; Francisco José Alfaro; José L. Sánchez 002; José Duato (Parallel and Distributed Computing and Networks, 2004)

QoS in InfiniBand Subnetworks. - Francisco José Alfaro; José L. Sánchez 002; José Duato (IEEE Trans. Parallel Distributed Syst., 2004)

Providing Full QoS Support in Clusters Using Only Two VCs at the Switches. - Alejandro Martínez; Francisco José Alfaro; José L. Sánchez 002; José Duato (HiPC, 2005)

Studying the Influence of the InfiniBand Packet Size to Guarantee QoS. - Francisco José Alfaro; José L. Sánchez 002; José Duato (ISCC, 2005)

Studying the Effect of the Design Parameters on the Interconnection Network Performance in NOWs. - Raúl Martínez; José L. Sánchez 002; Francisco José Alfaro; Vicente Chirivella; José Flich (PDP, 2005)

Towards a Cost-Effective Interconnection Network Architecture with QoS and Congestion Management Support. - Alejandro Martínez; Pedro Javier García; Francisco José Alfaro; José L. Sánchez 002; José Flich; Francisco J. Quiles 001; José Duato (Euro-Par, 2006)

Improving the Flexibility of the Deficit Table Scheduler. - Raúl Martínez; Francisco José Alfaro; José L. Sánchez 002 (HiPC, 2006)

QoS Support for Video Transmission in High-Speed Interconnects. - Alejandro Martínez; George Apostolopoulos; Francisco José Alfaro; José L. Sánchez 002; José Duato (HPCC, 2006)

Evaluating several implementations for the AS Minimum Bandwidth Egress Link Scheduler. - Raul Martinez-Morais; Francisco J. Alfaro-Cortes; José Luis Sánchez Garcia (ICCCN, 2006)

Providing Quality of Service over Advanced Switching. - Raúl Martínez; Francisco José Alfaro; José L. Sánchez 002 (ICPADS (1), 2006)

Scalable Low-Cost QoS Support for Single-chip Switches. - Alejandro Martínez; Francisco José Alfaro; José L. Sánchez 002; José Duato (ICPADS (1), 2006)

Decoupling the Bandwidth and Latency Bounding for Table-based Schedulers. - Raúl Martínez; Francisco José Alfaro; José L. Sánchez 002 (ICPP, 2006)

Studying Several Proposals for the Adaptation of the DTable Scheduler to Advanced Switching. - Raúl Martínez; Francisco José Alfaro; José L. Sánchez 002 (ISPA, 2006)

Implementing the Advanced Switching Minimum Bandwidth Egress Link Scheduler. - Raúl Martínez; Francisco José Alfaro; José L. Sánchez 002 (NCA, 2006)

Full QoS Support with 2 VCs for Single-chip Switches. - Alejandro Martínez; Francisco José Alfaro; José L. Sánchez 002; José Duato (NCA, 2006)

Integrated QoS Provision and Congestion Management for Interconnection Networks. - Alejandro Martínez-Vicente; Pedro Javier García; Francisco José Alfaro; José L. Sánchez 002; José Flich; Francisco J. Quiles 001; José Duato (Euro-Par, 2007)

Providing Full QoS with 2 VCs in High-Speed Switches. - Alejandro Martínez; Francisco José Alfaro; José L. Sánchez 002; José Duato (ICOIN, 2007)

Comparing the latency performance of the DTable and DRR schedulers. - Raúl Martínez; Francisco José Alfaro; José L. Sánchez 002 (IPDPS, 2007)

Deadline-based QoS Algorithms for High-performance Networks. - Alejandro Martínez; Francisco José Alfaro; José L. Sánchez 002; José Duato (IPDPS, 2007)

Efficient Switches with QoS Support for Clusters. - Alejandro Martínez; Francisco José Alfaro; José L. Sánchez 002; José Duato (IPDPS, 2007)

A low-cost strategy to provide full QoS support in Advanced Switching networks. - Alejandro Martínez; Raúl Martínez; Francisco José Alfaro; José L. Sánchez 002 (J. Syst. Archit., 2007)

A Formal Model to Manage the InfiniBand Arbitration Tables Providing QoS. - Francisco José Alfaro; José L. Sánchez 002; M. Menduiña; José Duato (IEEE Trans. Computers, 2007)

A New Cost-Effective Technique for QoS Support in Clusters. - Alejandro Martínez; Francisco José Alfaro; José L. Sánchez 002; Francisco J. Quiles 001; José Duato (IEEE Trans. Parallel Distributed Syst., 2007)

Efficient Deadline-Based QoS Algorithms for High-Performance Networks. - Alejandro Martínez-Vicente; George Apostolopoulos; Francisco José Alfaro; José L. Sánchez 002; José Duato (IEEE Trans. Computers, 2008)

A Framework to Provide Quality of Service over Advanced Switching. - Raúl Martínez; Francisco José Alfaro; José L. Sánchez 002 (IEEE Trans. Parallel Distributed Syst., 2008)

Hardware Implementation Study of the SCFQ-CA and DRR-CA Scheduling Algorithms. - Raúl Martínez; Francisco José Alfaro; José L. Sánchez 002; José M. Claver (Euro-Par, 2009)

Hardware Implementation Study of the Deficit Table Egress Link Scheduling Algorithm. - Raúl Martínez; José M. Claver; Francisco José Alfaro; José L. Sánchez 002 (ICPP, 2009)

A new strategy to manage the InfiniBand arbitration tables. - Francisco José Alfaro; José L. Sánchez 002; José Duato (J. Parallel Distributed Comput., 2009)

A Switch Architecture Guaranteeing QoS Provision and HOL Blocking Elimination. - Alejandro Martínez; Pedro Javier García; Francisco José Alfaro; José L. Sánchez 002; José Flich; Francisco J. Quiles 001; José Duato (IEEE Trans. Parallel Distributed Syst., 2009)

A GPU-Based DVC to H.264/AVC Transcoder. - Alberto Corrales-García; Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Gerardo Fernández-Escribano; José M. Claver; José Luis Sánchez Garcia (HAIS (2), 2010)

Providing QoS with the Deficit Table Scheduler. - Raul Martinez-Morais; Francisco J. Alfaro-Cortes; José L. Sánchez 002 (IEEE Trans. Parallel Distributed Syst., 2010)

A fast centralized computation routing algorithm for self-configuring NoC systems. - Francisco Triviño; Francisco José Alfaro; José L. Sánchez 002; José Flich (HiPC, 2011)

C-Switches: Increasing Switch Radix with Current Integration Scale. - Juan A. Villar; Francisco J. Andujar; José L. Sánchez 002; Francisco José Alfaro; José Duato (HPCC, 2011)

A GPU-Based Implementation for Range Queries on Spaghettis Data Structure. - Roberto Uribe Paredes; Pedro Valero-Lara; Enrique Arias 001; José L. Sánchez 002; Diego Cazorla (ICCSA (1), 2011)

Similarity search implementations for multi-core and many-core processors. - Roberto Uribe Paredes; Pedro Valero-Lara; Enrique Arias 001; José L. Sánchez 002; Diego Cazorla (HPCS, 2011)

Self-related traces: An alternative to full-system simulation for NoCs. - Francisco Triviño; Francisco J. Andujar; Francisco J. Alfaro; José L. Sánchez 002; Alberto Ros 001 (HPCS, 2011)

Reducing complexity in H.264/AVC motion estimation by using a GPU. - Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Gerardo Fernández-Escribano; José M. Claver; José L. Sánchez 002 (MMSP, 2011)

NoC Reconfiguration for CMP Virtualization. - Francisco Triviño; Francisco José Alfaro; José L. Sánchez 002; José Flich (NCA, 2011)

Evaluation of an Alternative for Increasing Switch Radix. - Juan A. Villar; Francisco J. Andujar; José L. Sánchez 002; Francisco José Alfaro; José Duato (NCA, 2011)

Virtualizing network-on-chip resources in chip-multiprocessors. - Francisco Triviño; José L. Sánchez 002; Francisco José Alfaro; José Flich (Microprocess. Microsystems, 2011)

A GPU-based implementation of the MRF algorithm in ITK package. - Pedro Valero-Lara; José L. Sánchez 002; Diego Cazorla; Enrique Arias 001 (J. Supercomput., 2011)

Improving the Performance for the Range Search on Metric Spaces Using a Multi-GPU Platform. - Roberto Uribe Paredes; Enrique Arias 001; José L. Sánchez 002; Diego Cazorla; Pedro Valero-Lara (DEXA (2), 2012)

A Fast GPU-Based Motion Estimation Algorithm for HD 3D Video Coding. - Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Gerardo Fernández-Escribano; José Luis Sánchez Garcia; José Manuel Claver (ISPA, 2012)

A Fast GPU-Based Motion Estimation Algorithm for H.264/AVC. - Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Gerardo Fernández-Escribano; José Luis Sánchez Garcia; José Manuel Claver (MMM, 2012)

Exploring NoC Virtualization Alternatives in CMPs. - Francisco Triviño; José L. Sánchez 002; Francisco José Alfaro; José Flich (PDP, 2012)

Optimal Configuration of High-Radix Combined Switches. - Juan A. Villar; Francisco J. Andujar; José L. Sánchez 002; Francisco José Alfaro; José Duato (PDP, 2012)

OSR-Lite: Fast and deadlock-free NoC reconfiguration framework. - Alessandro Strano; Davide Bertozzi; Francisco Triviño; José L. Sánchez 002; Francisco J. Alfaro; José Flich (ICSAMOS, 2012)

Optimizing H.264/AVC interprediction on a GPU-based framework. - Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Gerardo Fernández-Escribano; José L. Sánchez 002; José M. Claver; Pedro Diaz (Concurr. Comput. Pract. Exp., 2012)

Hardware implementation study of several new egress link scheduling algorithms. - Raúl Martínez; José M. Claver; Francisco J. Alfaro; José L. Sánchez 002 (J. Parallel Distributed Comput., 2012)

Network-on-Chip virtualization in Chip-Multiprocessor Systems. - Francisco Triviño; José L. Sánchez 002; Francisco J. Alfaro; José Flich (J. Syst. Archit., 2012)

Low delay H.264/AVC bidirectional inter prediction on a GPU. - Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Jan De Cock; José L. Sánchez 002; José M. Claver; Rik Van de Walle (ICIP, 2013)

3D high definition video coding on a GPU-based heterogeneous system. - Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Jan De Cock; Gerardo Fernández-Escribano; Bart Pieters; José L. Sánchez 002; José M. Claver; Rik Van de Walle (Comput. Electr. Eng., 2013)

Adapting hierarchical bidirectional inter prediction on a GPU-based platform for 2D and 3D H.264 video coding. - Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Jan De Cock; Gerardo Fernández-Escribano; Bart Pieters; José L. Sánchez 002; José Manuel Claver; Rik Van de Walle (EURASIP J. Adv. Signal Process., 2013)

Obtaining the optimal configuration of high-radix Combined switches. - Juan A. Villar; Francisco J. Andujar; José L. Sánchez 002; Francisco J. Alfaro; José A. Gámez 001; José Duato (J. Parallel Distributed Comput., 2013)

H.264/AVC inter prediction on accelerator-based multi-core systems. - Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Gerardo Fernández-Escribano; José Luis Sánchez Garcia; José Manuel Claver (Multim. Tools Appl., 2013)

A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs. - Alberto Ghiribaldi; Daniele Ludovici; Francisco Triviño; Alessandro Strano; José Flich; José L. Sánchez 002; Francisco J. Alfaro; Michele Favalli; Davide Bertozzi (ACM Trans. Embed. Comput. Syst., 2013)

H.264/AVC inter prediction for heterogeneous computing systems. - Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Gerardo Fernández-Escribano; José Manuel Claver; José L. Sánchez 002 (J. Supercomput., 2013)

An integrated solution for QoS provision and congestion management in high-performance interconnection networks using deterministic source-based routing. - Juan A. Villar; Pedro Javier García; Francisco José Alfaro; José L. Sánchez 002; Francisco J. Quiles 001 (J. Supercomput., 2013)

Deadlock-free routing mechanism for 3D twin torus networks. - Francisco J. Andújar; Juan A. Villar; Francisco J. Alfaro; José L. Sánchez 002; José Duato (INA-OCMC@HiPEAC, 2014)

Optimal Configuration for N-Dimensional Twin Torus Networks. - Francisco J. Andujar; Juan A. Villar; José L. Sánchez 002; Francisco J. Alfaro; José Duato (NCA, 2014)

Building 3D Torus Using Low-Profile Expansion Cards. - Francisco J. Andujar; Juan A. Villar; José L. Sánchez 002; Francisco J. Alfaro; José Duato (IEEE Trans. Computers, 2014)

Towards an efficient static scheduling scheme for delivering queries to heterogeneous clusters in the similarity search problem. - Roberto Uribe Paredes; Diego Cazorla; Enrique Arias 001; José L. Sánchez 002 (J. Supercomput., 2014)

Formalization and configuration methodology for high-radix combined switches. - Juan A. Villar; Francisco J. Andujar; Francisco J. Alfaro; José L. Sánchez 002; José Duato (J. Supercomput., 2014)

VEF Traces: A Framework for Modelling MPI Traffic in Interconnection Network Simulators. - Francisco J. Andujar; Juan A. Villar; José L. Sánchez 002; Francisco J. Alfaro; Jesús Escudero-Sahuquillo (CLUSTER, 2015)

N-Dimensional Twin Torus Topology. - Francisco J. Andujar-Munoz; Juan A. Villar-Ortiz; José L. Sánchez 002; Francisco José Alfaro; José Duato (IEEE Trans. Computers, 2015)

Optimizing the configuration of combined high-radix switches. - Juan A. Villar; Francisco J. Andujar; Francisco J. Alfaro; José L. Sánchez 002; José Duato (J. Supercomput., 2015)

Adaptive Routing for N-Dimensional Twin Torus. - Francisco J. Andujar; Juan A. Villar; José L. Sánchez 002; Francisco J. Alfaro; José Duato Marín (IEEE Trans. Computers, 2016)

An open-source family of tools to reproduce MPI-based workloads in interconnection network simulators. - Francisco J. Andujar; Juan A. Villar; Francisco J. Alfaro; José L. Sánchez 002; Jesús Escudero-Sahuquillo (J. Supercomput., 2016)

PhotoNoCs: Design Simulation Tool for Silicon Integrated Photonics Towards Exascale Systems. - Juan-José Crespo; Francisco J. Alfaro-Cortes; José L. Sánchez 002 (Euro-Par Workshops, 2017)

A Case Study on Implementing Virtual 5D Torus Networks Using Network Components of Lower Dimensionality. - Francisco J. Andujar; Juan A. Villar; José L. Sánchez 002; Francisco J. Alfaro; José Duato; Holger Fröning (HiPINEB@HPCA, 2017)

Acceleration of Moving Object Detection in Bio-Inspired Computer Vision. - José L. Sánchez 002; Raúl Viana; María T. López; Antonio Fernández-Caballero 001 (IWINAC (2), 2017)

Applying search algorithms to obtain the optimal configuration of nDT torus nodes. - Francisco J. Andujar-Munoz; Juan A. Villar-Ortiz; José Luis Sánchez Garcia; Francisco J. Alfaro-Cortes (Concurr. Comput. Pract. Exp., 2017)

GPU-based exhaustive algorithms processing kNN queries. - Ricardo J. Barrientos; Fabricio Millaguir; José L. Sánchez 002; Enrique Arias 001 (J. Supercomput., 2017)

An efficiency study of a pivot-based algorithm for similarity search on a heterogeneous platform. - Roberto Uribe Paredes; Enrique Arias 001; Diego Cazorla; José L. Sánchez 002 (J. Supercomput., 2017)

Analyzing Topology Parameters for Achieving Energy-Efficient k-ary n-cubes. - Francisco J. Andujar; Salvador Coll; Marina Alonso; Juan-Miguel Martínez 001; Pedro López 001; Francisco J. Alfaro; José L. Sánchez 002; Raúl Martínez (HiPINEB@HPCA, 2018)

VEF3 Traces: Towards a Complete Framework for Modelling Network Workloads for Exascale Systems. - Javier Cano-Cano; Francisco J. Andujar; Francisco J. Alfaro; José L. Sánchez 002 (HiPINEB@HPCA, 2018)

TopGen: A Library to Provide Simulation Tools with the Modeling of Interconnection Network Topologies. - Juan Antonio Villar; German Maglione Mathey; Jesús Escudero-Sahuquillo; Pedro Javier García; Francisco J. Alfaro; José Luis Sánchez Garcia; Francisco J. Quiles 001 (HPCS, 2018)

A Finite State Machine Approach to Algorithmic Lateral Inhibition for Real-Time Motion Detection. - María T. López; Aurelio Bermúdez; Francisco Montero Simarro; José L. Sánchez 002; Antonio Fernández-Caballero 001 (Sensors, 2018)

Methodology for Decoupled Simulation of SystemVerilog HDL Designs. - Juan-José Crespo; German Maglione Mathey; José L. Sánchez 002; Francisco J. Alfaro-Cortes; Jesús Escudero-Sahuquillo; Pedro Javier García; Francisco J. Quiles 001 (HPCS, 2019)

Constructing virtual 5-dimensional tori out of lower-dimensional network cards. - Francisco J. Andujar; Juan A. Villar; José L. Sánchez 002; Francisco J. Alfaro; José Duato; Holger Fröning (Concurr. Comput. Pract. Exp., 2019)

Silicon photonic networks: Signal loss and power challenges. - Juan-José Crespo; José L. Sánchez 002; Francisco J. Alfaro-Cortes (Concurr. Comput. Pract. Exp., 2019)

Energy efficient torus networks with on/off links. - Francisco J. Andújar; Salvador Coll; Marina Alonso; Juan-Miguel Martínez 001; Pedro López 001; José L. Sánchez 002; Francisco J. Alfaro; Raúl Martínez (J. Parallel Distributed Comput., 2019)

Speeding up exascale interconnection network simulations with the VEF3 trace framework. - Javier Cano-Cano; Francisco J. Andújar; Francisco J. Alfaro; José L. Sánchez 002 (J. Parallel Distributed Comput., 2019)

Accelerating bioinspired lateral interaction in accumulative computation for real-time moving object detection with graphics processing units. - José L. Sánchez 002; María T. López; José Manuel Pastor 001; Ana E. Delgado; Antonio Fernández-Caballero 001 (Nat. Comput., 2019)

Optimization of lateral interaction in accumulative computation on GPU-based platform. - Aurelio Bermúdez; Francisco Montero Simarro; María T. López; Antonio Fernández-Caballero 001; José L. Sánchez 002 (J. Supercomput., 2019)

Optimizing Packet Dropping by Efficient Congesting-Flow Isolation in Lossy Data-Center Networks. - Cristina Olmedilla; Jesús Escudero-Sahuquillo; Pedro Javier García; Francisco J. Alfaro-Cortés; Francisco J. Quiles 001; José L. Sánchez 002; Wenhao Sun; Xiang Yu; Yonghui Xu; José Duato (Hot Interconnects, 2020)

TDSR: Transparent Distributed Segment-Based Routing. - Juan-José Crespo; German Maglione Mathey; José L. Sánchez 002; Francisco J. Alfaro-Cortes; José Flich (CoRR, 2020)

Supporting Efficient Assignment of Medical Resources in Cancer Treatments with Simulation-Optimization. - Leandro do C. Martins; Juliana Castaneda; Angel A. Juan; Abtin Tondar; Laura Calvet; Barry B. Barrios; José Luis Sánchez Garcia (WSC, 2021)

QoS provision in hierarchical and non-hierarchical switch architectures. - Javier Cano-Cano; Francisco J. Andújar; Francisco J. Alfaro-Cortés; José L. Sánchez 002 (J. Parallel Distributed Comput., 2021)

DVL-Lossy: Isolating Congesting Flows to Optimize Packet Dropping in Lossy Data-Center Networks. - Cristina Olmedilla; Jesús Escudero-Sahuquillo; Pedro Javier García; Francisco J. Alfaro-Cortés; José L. Sánchez 002; Francisco J. Quiles 001; Wenhao Sun; Xiang Yu; Yonghui Xu; José Duato (IEEE Micro, 2021)

A methodology to enable QoS provision on InfiniBand hardware. - Javier Cano-Cano; Francisco J. Andújar; Jesús Escudero-Sahuquillo; Francisco J. Alfaro-Cortés; José L. Sánchez 002 (J. Supercomput., 2021)

UPR: deadlock-free dynamic network reconfiguration by exploiting channel dependency graph compatibility. - Juan-José Crespo; José L. Sánchez 002; Francisco J. Alfaro-Cortés; José Flich; José Duato (J. Supercomput., 2021)

Enabling Quality of Service Provision in Omni-Path Switches. - Javier Cano-Cano; Francisco J. Andújar; Francisco J. Alfaro-Cortés; José L. Sánchez 002 (Comput. Math. Methods, 2021)

RED-SEA: Network Solution for Exascale Architectures. - Andrea Biagioni; Paolo Cretaro; Ottorino Frezza; Francesca Lo Cicero; Alessandro Lonardo; Michele Martinelli; Pier Stanislao Paolucci; Elena Pastorelli; Francesco Simula; Matteo Turisini; Piero Vicini; Roberto Ammendola; et al. (DSD, 2022)

Providing quality of service in omni-path networks. - Javier Cano-Cano; Francisco J. Andújar; Francisco J. Alfaro-Cortés; José L. Sánchez 002; Gaspar Mora (J. Supercomput., 2022)

Energy efficient HPC network topologies with on/off links. - Francisco J. Andújar; Salvador Coll; Marina Alonso; Juan-Miguel Martínez 001; Pedro López 001; José L. Sánchez 002; Francisco J. Alfaro (Future Gener. Comput. Syst., 2023)

Using GPUs to simulate photovoltaic power plants: Special cases of performance loss. - Alberto Jiménez-Ruiz; Gerardo Fernández-Escribano; Miguel Cañas-Carretón; José L. Sánchez 002 (J. Comput. Sci., 2023)

Extending the VEF traces framework to model data center network workloads. - Francisco J. Andújar; Miguel Sánchez de la Rosa; Jesús Escudero-Sahuquillo; José L. Sánchez 002 (J. Supercomput., 2023)

Using graphics processing units for the efficient dynamic simulation of wind farms. - Alberto Jiménez-Ruiz; Gerardo Fernández-Escribano; Miguel Cañas-Carretón; José L. Sánchez 002 (Comput. Electr. Eng., 2023)

Quality-of-Service Provision for BXI3-Based Interconnection Networks. - Miguel Sánchez de la Rosa; Gabriel Gomez-Lopez; Francisco J. Andújar; Jesús Escudero-Sahuquillo; José L. Sánchez 002; Francisco J. Alfaro; Pierre-Axel Lagadec (HOTI, 2024)

RED-SEA Project: Towards a new-generation European interconnect. - María Engracia Gómez; Julio Sahuquillo; Andrea Biagioni; Nikos Chrysos; Damien Berton; Ottorino Frezza; Francesca Lo Cicero; Alessandro Lonardo; Michele Martinelli; Pier Stanislao Paolucci; Elena Pastorelli; Francesco Simula; et al. (Microprocess. Microsystems, 2024)

Quality-of-service provision for BXIv3-based interconnection networks. - Miguel Sánchez de la Rosa; Gabriel Gomez-Lopez; Francisco J. Andújar; Jesús Escudero-Sahuquillo; José L. Sánchez 002; Francisco J. Alfaro-Cortés; Pierre-Axel Lagadec (J. Supercomput., 2025)