Impact of spacer interface charges on performance and reliability of low temperature transistors for 3D sequential integration. - Tadeu Mota Frutuoso; Jose Lugo-Alvarez; Xavier Garros; Laurent Brunet; Joris Lacord; Louis Gerrer; Mikaël Cassé; Edoardo Catapano; Claire Fenouillet-Béranger; François Andrieu; Fred Gaillard; Philippe Ferrari (IRPS, 2021)

Ultra-fast CV methods (< 10µs) for interface trap spectroscopy and BTI reliability characterization using MOS capacitors. - Tadeu Mota Frutuoso; Xavier Garros; Jose Lugo-Alvarez; Roméo Kom Kammeugne; L. D. M. Zouknak; Abygaël Viey; W. van den Daele; Philippe Ferrari; Fred Gaillard (IRPS, 2022)

Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration. - Tadeu Mota Frutuoso; Xavier Garros; Perrine Batude; Laurent Brunet; Joris Lacord; Benoit Sklénard; V. Lapras; Claire Fenouillet-Béranger; M. Ribotta; A. Magalhaes-Lucas; J. Kanyandekwe; R. Kies; et al. (VLSI Technology and Circuits, 2022)

RF performance of Standard, High-Resistivity and Trap-Rich Silicon substrates down to cryogenic temperature. - Quentin Berlingard; M. Moulin; Jean-Philippe Michel; T. Fache; Ismael Charlet; C. Plantier; Z. Chalupa; Jose Lugo-Alvarez; Jean-Pierre Raskin; Louis Hutin; Mikaël Cassé (ESSDERC, 2023)