Implementation of Weighted Place/Transition Nets Based on Linear Enabling Functions. - José Luis Briz; José Manuel Colom (Application and Theory of Petri Nets, 1994)

Characterization and Improvement of Load/Store Cache-based Prefetching. - Pablo Ibáñez 001; Víctor Viñals; José Luis Briz; María Jesús Garzarán (International Conference on Supercomputing, 1998)

Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware. - María Jesús Garzarán; José Luis Briz; Pablo E. Ibáñez 001; Víctor Viñals (PDP, 2001)

Software Demand, Hardware Supply. - Jesús Alastruey; José Luis Briz; Pablo Ibáñez 001; Víctor Viñals (IEEE Micro, 2006)

Data prefetching in a cache hierarchy with high bandwidth and capacity. - Luis M. Ramos; José Luis Briz; Pablo E. Ibáñez 001; Víctor Viñals (SIGARCH Comput. Archit. News, 2007)

Low-Cost Adaptive Data Prefetching. - Luis M. Ramos; José Luis Briz; Pablo E. Ibáñez 001; Víctor Viñals (Euro-Par, 2008)

Multi-level Adaptive Prefetching based on Performance Gradient Tracking. - Luis M. Ramos; José Luis Briz; Pablo E. Ibáñez 001; Víctor Viñals (J. Instr. Level Parallelism, 2011)

An energy efficient GPGPU memory hierarchy with tiny incoherent caches. - Alamelu Sankaranarayanan; Ehsan K. Ardestani; José Luis Briz; Jose Renau (ISLPED, 2013)

On-line scheduling in multiprocessor systems based on continuous control using Timed Continuous Petri Nets. - Gaddiel Desirena-Lopez; Carlos Renato Vázquez; José Luis Briz; Antonio Ramírez-Treviño; David Gómez-Gutiérrez (WODES, 2016)

Managing Mismatches in Voltage Stacking with CoreUnfolding. - Ehsan K. Ardestani; Rafael Trapani Possignolo; José Luis Briz; Jose Renau (ACM Trans. Archit. Code Optim., 2016)

Accelerating Board Games Through Hardware/Software Codesign. - Javier Olivito; Javier Resano; José Luis Briz (IEEE Trans. Comput. Intell. AI Games, 2017)

GPU NTC Process Variation Compensation With Voltage Stacking. - Rafael Trapani Possignolo; Elnaz Ebrahimi 001; Ehsan K. Ardestani; Alamelu Sankaranarayanan; José Luis Briz; Jose Renau (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Exposing Abstraction-Level Interactions with a Parallel Ray Tracer. - Alejandro Valero; Darío Suárez Gracia; Ruben Gran Tejero; Luis M. Ramos; Agustín Navarro-Torres; Adolfo Muñoz 001; Joaquín Ezpeleta; José Luis Briz; Ana C. Murillo; Eduardo Montijano; Javier Resano; María Villarroya-Gaudó; et al. (WCAE@ISCA, 2019)

A Flexible Framework for Real-Time Thermal-Aware Schedulers using Timed Continuous Petri Nets. - Gaddiel Desirena-Lopez; Laura Elena Rubio Anguiano; Antonio Ramírez-Treviño; José Luis Briz (Computación y Sistemas, 2019)

Energy-efficient thermal-aware multiprocessor scheduling for real-time tasks using TCPN. - Laura Elena Rubio Anguiano; Gaddiel Desirena-Lopez; Antonio Ramírez-Treviño; José Luis Briz (Discret. Event Dyn. Syst., 2019)

Thermal-aware Real-time Scheduling Using Timed Continuous Petri Nets. - Gaddiel Desirena-Lopez; Antonio Ramírez-Treviño; José Luis Briz; Carlos Renato Vázquez; David Gómez-Gutiérrez (ACM Trans. Embed. Comput. Syst., 2019)

Maximizing Utilization and Minimizing Migration in Thermal-Aware Energy-Efficient Real-Time Multiprocessor Scheduling. - Laura Elena Rubio Anguiano; Abel Chils Trabanco; José Luis Briz Velasco; Antonio Ramírez-Treviño (IEEE Access, 2021)

Accounting for Preemption and Migration Costs in the Calculation of Hard Real-Time Cyclic Executives for MPSoCs. - Laura Elena Rubio Anguiano; José Luis Briz; Antonio Ramírez-Treviño (IEEE Robotics Autom. Lett., 2022)

Fast IEEE802.1Qbv Gate Scheduling Through Integer Linear Programming. - Alitzel Galilea Torres-Macías; Juan Segarra Flor; José Luis Briz Velasco; Antonio Ramírez-Treviño; Héctor Blanco-Alcaine (IEEE Access, 2024)

Characterization of latency and jitter in TSN emulation. - Álex Gracia; José Luis Briz; Héctor Blanco-Alcaine; Juan Segarra; Alitzel Galilea Torres-Macías; Antonio Ramírez-Treviño (CoRR, 2025)