A design methodology for logic paths tolerant to local intra-die variations. - Daniel Iparraguirre-Cardenas; Jose Luis Garcia-Gervacio; Víctor H. Champac (ISCAS, 2008)

Detectability analysis of small delays due to resistive opens considering process variations. - Jose Luis Garcia-Gervacio; Víctor H. Champac (IOLTS, 2009)

Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs. - Jose Luis Garcia-Gervacio; Víctor H. Champac (ETS, 2010)

Computing the Detection Probability for Small Delay Defects of Nanometer ICs. - Jose Luis Garcia-Gervacio; Víctor H. Champac (J. Electron. Test., 2011)

Small-delay defects detection under process variation using Inter-Path Correlation. - Francisco J. Galarza-Medina; Jose Luis Garcia-Gervacio; Víctor H. Champac; Alex Orailoglu (VTS, 2012)

Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias. - Hector Villacorta; Jose Luis Garcia-Gervacio; Víctor H. Champac; Sebastià A. Bota; Jaime Martínez-Castillo; Jaume Segura 001 (LATW, 2013)

Voltage Regulation System for UHF RFID Tags. - Jose Luis Garcia-Gervacio; Agustín Leobardo Herrera-May; Gregorio Zamora-Mejía; Jaime Martínez-Castillo; Alejandro Díaz-Sánchez (SBCCI, 2013)

Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies. - Jose Luis Garcia-Gervacio; Jaime Martínez-Castillo; Víctor H. Champac (LATW, 2014)

Low VDD and body bias conditions for testing bridge defects in the presence of process variations. - Hector Villacorta; Jose Luis Garcia-Gervacio; Jaume Segura 001; Víctor H. Champac (Microelectron. J., 2015)

Screening small-delay defects using inter-path correlation to reduce reliability risk. - Jose Luis Garcia-Gervacio; Alejandro Nocua; Víctor H. Champac (Microelectron. Reliab., 2015)

SCADA system design: A proposal for optimizing a production line. - Jose Adrian Ruiz Carmona; Julio Cesar Munoz Benitez; Jose Luis Garcia-Gervacio (CONIELECOMP, 2016)

TCAD analysis and modeling for NBTI mechanism in FinFET transistors. - Alfonso Herrera-Moreno; Jose Luis Garcia-Gervacio; Héctor Villacorta-Minaya; Héctor Vázquez-Leal (IEICE Electron. Express, 2018)

Exploring a homotopy approach for the design of nanometer digital circuits tolerant to process variations. - Gilberto Domínguez Rodríguez; Jose Luis Garcia-Gervacio; Héctor Vázquez-Leal (IEICE Electron. Express, 2018)