An Improved Path Enumeration Method Considering Different Fall and Rise Gate Delays. - José Luís Güntzel; Ana Cristina Medina Pinto; Fernando Moraes 001; Ricardo Reis 001 (SBCCI, 1998)

Designing a Mask Programmable Matrix for Sequential Circuits. - Fernanda Lima 001; Marcelo O. Johann; José Luís Almada Güntzel; Eduardo D'Avila; Luigi Carro; Ricardo Augusto da Luz Reis (VLSI, 1999)

ATG-Based Timing Analysis of Circuits Containing Complex Gates. - José Luís Güntzel; Ana Cristina Medina Pinto; Eduardo D'Avila; Ricardo Reis 001 (SBCCI, 2000)

A Timed Calculus for ATG-Based Timing Analysis with Complex Gates. - José Luís Güntzel; Ana Cristina Medina Pinto; Ricardo Reis 001 (LATW, 2001)

Análise de Timing Funcional de Circuitos VLSI Contendo Portas Complexas. - José Luís Almada Güntzel; Ricardo Augusto da Luz Reis (RITA, 2001)

A Comparison Between Testability Measures Applied to Complex Gates. - José Luís Güntzel; Gustavo Wilke; Márcio Bystronski; Ana Cristina Medina Pinto; Ricardo Reis 001 (LATW, 2002)

Finding the Critical Delay of Combinational Blocks by Floating Vector Simulation and Path Tracing. - Gustavo Wilke; José Luís Güntzel; Márcio Bystronski; Ana Cristina Medina Pinto; Ricardo Reis 001 (SBCCI, 2002)

Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. - David Guerrero Martos; Gustavo Wilke; José Luís Almada Güntzel; Manuel J. Bellido; Jorge Juan-Chico; Paulino Ruiz-de-Clavijo; Alejandro Millán 001 (PATMOS, 2003)

Improving Critical Path Identification in Functional Timing Analysis. - Daniel Lima Ferrão; Gustavo Wilke; Ricardo Augusto da Luz Reis; José Luís Almada Güntzel (SBCCI, 2003)

A Transistor Sizing Method Applied to an Automatic Layout Generation Tool. - Cristiano Santos; Gustavo Wilke; Cristiano Lazzari; Ricardo Reis 001; José Luís Almada Güntzel (SBCCI, 2003)

A New Macro-cell Generation Strategy for three metal layer CMOS Technologies. - Cristiano Lazzari; Cristiano Viana Domingues; José Luís Almada Güntzel; Ricardo Augusto da Luz Reis (VLSI-SOC, 2003)

A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits. - Cristiano Lazzari; Cristiano Viana Domingues; José Luís Güntzel; Ricardo Reis 001 (VLSI-SoC (Selected Papers), 2003)

Physical design methodologies for performance predictability and manufacturability. - Ricardo Reis 001; Fernanda Lima Kastensmidt; José Luís Almada Güntzel (Conf. Computing Frontiers, 2004)

A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool. - Fabricio B. Bastian; Cristiano Lazzari; José Luís Almada Güntzel; Ricardo Reis 001 (PATMOS, 2004)

Incremental timing optimization for automatic layout generation. - Cristiano Santos; Daniel Lima Ferrão; Ricardo Reis 001; José Luís Güntzel (ISCAS (4), 2005)

High throughput architecture for H.264/AVC forward transforms block. - Luciano Volcan Agostini; Roger Endrigo Carvalho Porto; Sergio Bampi; Leandro Rosa; José Luís Güntzel; Ivan Saraiva Silva (ACM Great Lakes Symposium on VLSI, 2006)

High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard. - Luciano Volcan Agostini; Roger Endrigo Carvalho Porto; José Luís Güntzel; Ivan Saraiva Silva; Sergio Bampi (ISCAS, 2006)

Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis. - Daniel Lima Ferrão; Ricardo Reis 001; José Luís Almada Güntzel (PATMOS, 2006)

RIC Fast Adder and its Set Tolerant Implementation in FPGAs. - Eduardo Mesquita; Helen Franck; Luciano Volcan Agostini; José Luís Güntzel (FPL, 2007)

Mapping Data and Code into Scratchpads from Relocatable Binaries. - Alexandre Keunecke Ignácio Mendonça; Daniel P. Volpato; José Luís Almada Güntzel; Luiz C. V. dos Santos (ISVLSI, 2009)

A Post-compiling Approach that Exploits Code Granularity in Scratchpads to Improve Energy Efficiency. - Daniel P. Volpato; Alexandre Keunecke Ignácio Mendonça; Luiz C. V. dos Santos; José Luís Almada Güntzel (ISVLSI, 2010)

A1CSA: An energy-efficient fast adder architecture for cell-based VLSI design. - Jucemar Monteiro; José Luís Güntzel; Luciano Volcan Agostini (ICECS, 2011)

An energy-efficient 8×8 2-D DCT VLSI architecture for battery-powered portable devices. - Vinicius S. Livramento; Bruno George de Moraes; Brunno Abner Machado; José Luís Güntzel (ISCAS, 2011)

An energy-efficient FDCT/IDCT configurable IP core for mobile multimedia platforms. - Vinicius S. Livramento; Bruno George de Moraes; Brunno Abner Machado; José Luís Almada Güntzel (SBCCI, 2011)

Cache-tuning-aware scratchpad allocation from binaries. - Daniel P. Volpato; Alexandre Keunecke Ignácio Mendonça; José Luís Almada Güntzel; Luiz Cláudio Villar dos Santos (SBCCI, 2011)

Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization. - Vinicius dos S. Livramento; Chrystian Guth; José Luís Güntzel; Marcelo O. Johann (ICECS, 2012)

Energy-efficient multi-task computing on MPSoCs: A case study from a memory perspective. - Rafael Westphal; José Luís Almada Güntzel; Luiz Cláudio Villar dos Santos (ICECS, 2012)

Fast and efficient lagrangian relaxation-based discrete gate sizing. - Vinicius S. Livramento; Chrystian Guth; José Luís Güntzel; Marcelo O. Johann (DATE, 2013)

Quality assessment of subsampling patterns for pel decimation targeting high definition video. - Ismael Seidel; Bruno George de Moraes; Emilio Wuerges; José Luís Almada Güntzel (ICME, 2013)

A low-power configurable VLSI architecture for sum of absolute differences calculation. - Ismael Seidel; Bruno George de Moraes; José Luís Güntzel (LASCAS, 2013)

VLSI architectures for Digital Modulation Classification using Support Vector Machines. - Edson Sorato; Renan Netto; Pedro Michel; José Luís Güntzel; Adalbery R. Castro; Aldebaro Klautau (LASCAS, 2013)

On the impacts of pel decimation and High-Vt/Low-Vdd on SAD calculation. - Ismael Seidel; Bruno George de Moraes; André Beims Bräscher; José Luís Güntzel (SBCCI, 2013)

Real-time digital modulation classification based on Support Vector Machines. - Edson Sorato; Eduardo P. Fronza; Paulo R. F. M. M. Barbosa; José Luís Almada Güntzel; Adalbery R. Castro; Aldebaro Klautau (SBCCI, 2013)

Energy-Efficient Hadamard-Based SATD Architectures. - Luiz Henrique Cancellier; André Beims Bräscher; Ismael Seidel; José Luís Güntzel (SBCCI, 2014)

A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation. - Vinicius S. Livramento; Chrystian Guth; José Luís Almada Güntzel; Marcelo O. Johann (ACM Trans. Design Autom. Electr. Syst., 2014)

Exploiting Non-Critical Steiner Tree Branches for Post-Placement Timing Optimization. - Vinicius S. Livramento; Chrystian Guth; Renan Netto; José Luís Almada Güntzel; Luiz C. V. dos Santos (ICCAD, 2015)

Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression. - Chrystian Guth; Vinicius S. Livramento; Renan Netto; Renan Fonseca; José Luís Güntzel; Luiz C. V. dos Santos (ISPD, 2015)

An analytical timing-driven algorithm for detailed placement. - Jucemar Monteiro; Guilherme Flach; Marcelo O. Johann; José Luís Almada Güntzel (LASCAS, 2015)

Combining Pel Decimation with Partial Distortion Elimination to increase SAD energy efficiency. - Ismael Seidel; André Beims Bräscher; José Luís Güntzel (PATMOS, 2015)

Exploiting parallelism to speed up circuit legalization. - Renan Netto; Chrystian Guth; Vinicius S. Livramento; Márcio Castro 001; Laércio Lima Pilla; José Luís Güntzel (ICECS, 2016)

Coarse grain partial distortion elimination for Hadamard ME in HEVC. - Ismael Seidel; José Luís Güntzel; Luciano Volcan Agostini (ICECS, 2016)

Rate-constrained successive elimination of Hadamard-based SATDs. - Ismael Seidel; Luiz Henrique Cancellier; José Luís Almada Güntzel; Luciano Volcan Agostini (ICIP, 2016)

Energy-efficient SATD for beyond HEVC. - Ismael Seidel; André Beims Bräscher; José Luís Almada Güntzel; Luciano Volcan Agostini (ISCAS, 2016)

Speeding up Incremental Legalization with Fast Queries to Multidimensional Trees. - Renan Netto; Vinicius S. Livramento; Chrystian Guth; Luiz C. V. dos Santos; José Luís Güntzel (ISVLSI, 2016)

Squarer exploration for energy-efficient sum of squared differences. - Ismael Seidel; Marcio Monteiro; José Luís Almada Güntzel; Luciano Volcan Agostini (LASCAS, 2016)

Evaluating the impact of circuit legalization on incremental optimization techniques. - Renan Netto; Vinicius S. Livramento; Chrystian Guth; Luiz C. V. dos Santos; José Luís Güntzel (SBCCI, 2016)

Clock-Tree-Aware Incremental Timing-Driven Placement. - Vinicius S. Livramento; Renan Netto; Chrystian Guth; José Luís Güntzel; Luiz Cláudio Villar dos Santos (ACM Trans. Design Autom. Electr. Syst., 2016)

How Game Engines Can Inspire EDA Tools Development: A use case for an open-source physical design library. - Tiago Fontana; Renan Netto; Vinicius S. Livramento; Chrystian Guth; Sheiny Almeida; Laércio Lima Pilla; José Luís Güntzel (ISPD, 2017)

Improving the energy efficiency of a low-area SATD hardware architecture using fine grain PDE. - André Beims Bräscher; Ismael Seidel; José Luís Güntzel (SBCCI, 2017)

Block matching hardware architecture for SATD-based successive elimination. - Luiz Henrique Cancellier; Ismael Seidel; José Luís Güntzel (SBCCI, 2017)

Exploiting cache locality to speedup register clustering. - Tiago Augusto Fontana; Sheiny Almeida; Renan Netto; Vinicius S. Livramento; Chrystian Guth; Laércio Lima Pilla; José Luís Güntzel (SBCCI, 2017)

Incremental Layer Assignment Driven by an External Signoff Timing Engine. - Vinicius S. Livramento; Derong Liu 002; Salim Chowdhury; Bei Yu 001; Xiaoqing Xu; David Z. Pan; José Luís Almada Güntzel; Luiz C. V. dos Santos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

On HEVC Robustness to Integer Motion Estimation Pruning. - Luiz Henrique Cancellier; Ismael Seidel; José Luís Güntzel (ICECS, 2018)

A Domain-specific Language for Automated Fault Injection in SystemC Models. - Douglas Lohmann; Alexis Huf; Djones Lettnin; Frank Siqueira; José Luís Güntzel (ICECS, 2018)

Coding- and Energy-Efficient FME Hardware Design. - Ismael Seidel; Vanio Rodrigues Filho; Luciano Volcan Agostini; José Luís Güntzel (ISCAS, 2018)

On the calculation reuse in hadamard-based SATD. - Marcio Monteiro; Ismael Seidel; José Luís Güntzel (LASCAS, 2018)

Enhancing Multi-Threaded Legalization Through k-d Tree Circuit Partitioning. - Sheiny Fabre; José Luís Güntzel; Laércio Lima Pilla; Renan Netto; Tiago Fontana; Vinicius S. Livramento (SBCCI, 2018)

How Deep Learning Can Drive Physical Synthesis Towards More Predictable Legalization. - Renan Netto; Sheiny Fabre; Tiago Augusto Fontana; Vinicius S. Livramento; Laércio Lima Pilla; José Luís Güntzel (ISPD, 2019)

Energy-Efficient Hadamard-Based SATD Hardware Architectures Through Calculation Reuse. - Ismael Seidel; Marcio Monteiro; Bruno Bonotto; Luciano Volcan Agostini; José Luís Güntzel (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Standalone Rate-Distortion FME Architecture. - Vanio Rodrigues Filho; Marcio Monteiro; Ismael Seidel; Mateus Grellert; José Luís Güntzel (SBCCI, 2020)

Guest Editors' Introduction: SBCCI 2018. - Michael Hübner 001; José Luís Güntzel (IEEE Des. Test, 2020)

Relying on a Rate Constraint to Reduce Motion Estimation Complexity. - Gabriel B. Sant'Anna; Luiz Henrique Cancellier; Ismael Seidel; Mateus Grellert; José Luís Güntzel (ICASSP, 2021)

Design of Energy-Efficient Gaussian Filters by Combining Refactoring and Approximate Adders. - Marcio Monteiro; Pedro Aquino Silva; Ismael Seidel; Mateus Grellert; Leonardo Bandeira Soares; José Luís Güntzel; Cristina Meinhardt (ISCAS, 2021)

ILP-Based Global Routing Optimization with Cell Movements. - Tiago Augusto Fontana; Erfan Aghaeekiasaraee; Renan Netto; Sheiny Fabre Almeida; Upma Gandhi; Aysa Fakheri Tabrizi; David T. Westwick; Laleh Behjat; José Luís Güntzel (ISVLSI, 2021)

Hardware-Friendly Search Patterns for the Versatile Video Coding Fractional Motion Estimation. - Vanio Rodrigues Filho; Marcio Monteiro; Ismael Seidel; Mateus Grellert; José Luís Güntzel (MMSP, 2021)

SAD or SATD? How the Distortion Metric Impacts a Fractional Motion Estimation VLSI Architecture. - Ismael Seidel; Vanio Rodrigues Filho; Mateus Grellert; Luciano Volcan Agostini; José Luís Güntzel (MMSP, 2021)

Autoencoder Model Exploration for Multi-Layer Video Compression. - Luiz Henrique Cancellier; Mateus Grellert; José Luís Güntzel; Luís Alberto da Silva Cruz (EUVIP, 2022)

E-RVP: An Initial Design Rule Violation Predictor Using Placement Information. - Sheiny Fabre Almeida; Aysa Fakheri Tabrizi; Erfan Aghaeekiasaraee; Renan Netto; Tiago Augusto Fontana; Upma Gandhi; José Luís Güntzel; Laleh Behjat; Cristina Meinhardt (ICECS 2022, 2022)

Exploring the Impacts of Multiple Kernel Sizes of Gaussian Filters Combined to Approximate Computing in Canny Edge Detection. - Marcio Monteiro; Ismael Seidel; Mateus Grellert; José Luís Güntzel; Leonardo Bandeira Soares; Cristina Meinhardt (LASCAS, 2022)

Routability-Driven Detailed Placement Using Reinforcement Learning. - Sheiny Fabre Almeida; José Luís Güntzel; Laleh Behjat; Cristina Meinhardt (VLSI-SoC, 2022)

Algorithm Selection Framework for Legalization Using Deep Convolutional Neural Networks and Transfer Learning. - Renan Netto; Sheiny Fabre; Tiago Augusto Fontana; Vinicius S. Livramento; Laércio Lima Pilla; Laleh Behjat; José Luís Güntzel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A New Approach to Video Coding Leveraging Hybrid Coding and Video Frame Interpolation. - André Beims Bräscher; Gabriela Furtado Da Silveira; Luiz Henrique Cancellier; Ismael Seidel; Mateus Grellert; José Luís Güntzel (SBCCI, 2023)

Low-Energy and Reduced-Area Hardware Architecture for the Versatile Video Coding FME. - Vanio Rodrigues Filho; Ismael Seidel; Nicole Citadin; Marcio Monteiro; Mateus Grellert; José Luís Güntzel (SBCCI, 2023)

CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes. - Erfan Aghaeekiasaraee; Aysa Fakheri Tabrizi; Tiago Augusto Fontana; Renan Netto; Sheiny Fabre Almeida; Upma Gandhi; José Luís Güntzel; David T. Westwick; Laleh Behjat (ACM Trans. Design Autom. Electr. Syst., 2023)

A Dual-Kernel Size-Configurable Gaussian Filter Architecture. - Marcio Monteiro; Ismael Seidel; José Luís Güntzel; Mateus Grellert; Leonardo Bandeira Soares; Cristina Meinhardt (SBCCI, 2024)

ILPGRC: ILP-Based Global Routing Optimization With Cell Movements. - Tiago Augusto Fontana; Erfan Aghaeekiasaraee; Renan Netto; Sheiny Fabre Almeida; Upma Gandhi; Laleh Behjat; José Luís Güntzel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

GRCMO: Global Routing Optimization by Median-Based Cell Movement. - Arthur Lourenco; Felipe Savi; Felipe Nascimento; Erfan Aghaeekiasaraee; Upma Gandhi; Renan Netto; Laleh Behjat; Tiago Augusto Fontana; José Luís Güntzel (LASCAS, 2025)

A Parallel JPEG Pleno Baseline Block-Based Profile Light Field Encoder Using OpenMP. - Ismael Seidel; André Filipe da Silva Fernandes; José Luís Güntzel (LASCAS, 2025)

Markov Modeling of Video Coding Prediction Residue for Transform Hardware Power Analysis. - João Marcos Marqueti; Gustavo Russi; Ismael Seidel; José Luís Güntzel (NewCAS, 2025)

Asymmetric Multi-Layer Compression: Decoupling Inter-Layer Coding Dependencies With a Learned Model. - Luiz Henrique Cancellier; André Beims Bräscher; Ismael Seidel; Mateus Grellert; Luís Alberto da Silva Cruz; José Luís Güntzel (IEEE Access, 2025)

Eh-DRVP: Combining placement and global routing data in a hyper-image-based DRV predictor. - Sheiny Fabre Almeida; Renan Netto; Tiago Augusto Fontana; Erfan Aghaeekiasaraee; Upma Gandhi; Aysa Fakheri Tabrizi; José Luís Güntzel; Laleh Behjat; Cristina Meinhardt (Integr., 2025)