A New Reconfigurable-Oriented Method for Canonical Basis Multiplication over a Class of Finite Fields GF(2m). - José Luis Imaña; Juan Manuel Sánchez (FPL, 2003)

Reconfigurable implementation of bit-parallel multipliers over GF(2m) for two classes of finite fields. - José Luis Imaña (FPT, 2004)

Bit-Parallel Finite Field Multipliers for Irreducible Trinomials. - José Luis Imaña; Juan Manuel Sánchez; Francisco Tirado (IEEE Trans. Computers, 2006)

Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials. - José Luis Imaña; Román Hermida; Francisco Tirado (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields GF(2m) Generated by AOPs. - José Luis Imaña; Juan Manuel Sánchez (J. VLSI Signal Process., 2006)

Efficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial Computation. - Gustavo Sutter; Jean-Pierre Deschamps; José Luis Imaña (FPL, 2010)

Probabilistic Verification over GF(2m) Using Mod2-OBDDs. - José Luis Imaña (Intell. Inf. Manag., 2010)

Low Latency GF(2m) Polynomial Basis Multiplier. - José Luis Imaña (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Modular Multiplication and Exponentiation Architectures for Fast RSA Cryptosystem Based on Digit Serial Computation. - Gustavo Sutter; Jean-Pierre Deschamps; José Luis Imaña (IEEE Trans. Ind. Electron., 2011)

Efficient Polynomial Basis Multipliers for Type-II Irreducible Pentanomials. - José Luis Imaña (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials. - José Luis Imaña; Román Hermida; Francisco Tirado (Integr., 2013)

Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations. - Gustavo Sutter; Jean-Pierre Deschamps; José Luis Imaña (IEEE Trans. Ind. Electron., 2013)

High-Speed Polynomial Basis Multipliers Over GF(2m) for Special Pentanomials. - José Luis Imaña (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Reconfigurable implementation of GF(2m) bit-parallel multipliers. - José Luis Imaña (DATE, 2018)

Efficient FPGA Implementation of Binary Field Multipliers Based on Irreducible Trinomials. - José Luis Imaña (FCCM, 2018)

Fast Bit-Parallel Binary Multipliers Based on Type-I Pentanomials. - José Luis Imaña (IEEE Trans. Computers, 2018)

FPGA Implementation of Post-Quantum DME Cryptosystem. - José Luis Imaña; Ignacio Luengo (FCCM, 2020)

High-throughput architecture for post-quantum DME cryptosystem. - José Luis Imaña; Ignacio Luengo (Integr., 2020)

Optimized reversible quantum circuits for ${ mathbb {F}}_{2^8}$ multiplication. - José Luis Imaña (Quantum Inf. Process., 2021)

LFSR-Based Bit-Serial GF(2m) Multipliers Using Irreducible Trinomials. - José Luis Imaña (IEEE Trans. Computers, 2021)

Low-Delay FPGA-Based Implementation of Finite Field Multipliers. - José Luis Imaña (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography. - Tianyou Bao; José Luis Imaña; Pengzhou He; Jiafeng Xie (CODES+ISSS, 2022)

Decomposition of Dillon's APN Permutation with Efficient Hardware Implementation. - José Luis Imaña; Lilya Budaghyan; Nikolay S. Kaleyski (WAIFI, 2022)

Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography. - José Luis Imaña; Pengzhou He; Tianyou Bao; Yazheng Tu; Jiafeng Xie (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Efficient Hardware Implementation of Finite Field Arithmetic $AB+C$AB+C for Binary Ring-LWE Based Post-Quantum Cryptography. - Jiafeng Xie; Pengzhou He; Xiaofang Wang; José Luis Imaña (IEEE Trans. Emerg. Top. Comput., 2022)

Hardware architecture of Dillon's APN permutation for different primitive polynomials. - José Luis Imaña; Nikolay S. Kaleyski; Lilya Budaghyan (Microprocess. Microsystems, 2023)

Domain-oriented masked bit-parallel finite-field multiplier against side-channel attacks. - José Luis Imaña; Siemen Dhooghe (Inf. Process. Lett., 2023)

Integrating Post-Quantum Cryptography Plugins for IPsec Offloads to Data Processing Units in the Cloud-Edge Continuum. - Abraham Cano Aguilera; Carlos Rubio Garcia; Raphaël Frantz; Idelfonso Tafur Monroy; José Luis Imaña; Juan José Vegas Olmos (ICNP, 2024)

The zero-tax data center: a use case through quantum resilient communications. - Daniel C. Lawo; Michal Podles; Raphael Frantz; Abraham Cano Aguilera; Dimosthenis Iliadis-Apostolidis; Jerónimo Sánchez García; Sokol Kosta; Idelfonso Tafur Monroy; José Luis Imaña; J. J. Vegas Olmos (ICTON, 2024)

First Line-rate End-to-End Post-Quantum Encrypted Optical Fiber Link Using Data Processing Units (DPUs). - Abraham Cano Aguilera; Rana Abu Bakar; Faris Alhamed; Carlos Rubio Garcia; José Luis Imaña; Idelfonso Tafur Monroy; Filippo Cugini; J. J. Vegas Olmos (OFC, 2024)

Falcon/Kyber and Dilithium/Kyber Network Stack on Nvidia's Data Processing Unit Platform. - Daniel C. Lawo; Raphael Frantz; Abraham Cano Aguilera; X. Arnal I Clemente; M. P. Podles; José Luis Imaña; Idelfonso Tafur Monroy; J. J. Vegas Olmos (IEEE Access, 2024)

Wireless and Fiber-Based Post-Quantum-Cryptography-Secured IPsec Tunnel. - Daniel C. Lawo; Rana Abu Bakar; Abraham Cano Aguilera; Filippo Cugini; José Luis Imaña; Idelfonso Tafur Monroy; Juan Jose Vegas Olmos (Future Internet, 2024)

Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration. - José Luis Imaña; Luis Piñuel; Yao-Ming Kuo; Oscar Ruano; Francisco Garcia-Herrero (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Low-Complexity Hardware Architecture of APN Permutations Using TU-Decomposition. - Lilya Budaghyan; José Luis Imaña; Nikolay S. Kaleyski (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

First Demonstration of 200 Gbps Regime Line-Rate Quantum-Secure MACsec Optical Links Using Commodity Hardware Offloads. - Abraham Cano Aguilera; Carlos Rubio Garcia; Daniel C. Lawo; Idelfonso Tafur Monroy; José Luis Imaña; J. J. Vegas Olmos (OFC, 2025)

ARM Architecture Optimizations for Line-Rate PQC Communications. - Abraham Cano Aguilera; Idelfonso Tafur Monroy; J. J. Vegas Olmos; José Luis Imaña (ONDM, 2025)