A variable threshold voltage inverter for CMOS programmable logic circuits. - Jaume Segura 001; José Luis Rosselló; J. Morra; H. Sigg (IEEE J. Solid State Circuits, 1998)

Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization. - José Luis Rosselló; Jaume Segura 001 (ICCAD, 2001)

A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers. - José Luis Rosselló; Jaume Segura 001 (PATMOS, 2002)

Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers. - José Luis Rosselló; Jaume Segura 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates. - José Luis Rosselló; Jaume Segura 001 (PATMOS, 2003)

Structural RFIC device testing through built-in thermal monitoring. - Josep Altet; Antonio J. Rubio; José Luis Rosselló; Jaume Segura 001 (IEEE Commun. Mag., 2003)

A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk. - José Luis Rosselló; Jaume Segura 001 (DATE, 2004)

Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism. - Sebastià A. Bota; M. Rosales; José Luis Rosselló; Jaume Segura 001; Ali Keshavarzi (ITC, 2004)

An analytical charge-based compact delay model for submicrometer CMOS inverters. - José Luis Rosselló; Jaume A. Segura 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

Smart Temperature Sensor for Thermal Testing of Cell-Based ICs. - Sebastià A. Bota; M. Rosales; José Luis Rosselló; Jaume Segura 001 (DATE, 2005)

A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. - José Luis Rosselló; Vicent Canals; Sebastià A. Bota; Ali Keshavarzi; Jaume Segura 001 (DATE, 2005)

Compact Static Power Model of Complex CMOS Gates. - José Luis Rosselló; Sebastià A. Bota; Jaume Segura 001 (PATMOS, 2005)

A compact gate-level energy and delay model of dynamic CMOS gates. - José Luis Rosselló; Carol de Benito; Jaume Segura 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

A compact model to identify delay faults due to crosstalk. - José Luis Rosselló; Jaume Segura 001 (DATE, 2006)

A Fully CMOS Low-Cost Chaotic Neural Network. - José Luis Rosselló; Sebastià A. Bota; Vicent Canals; Ivan de Paúl; Jaume Segura 001 (IJCNN, 2006)

Leakage Power Characterization Considering Process Variations. - José Luis Rosselló; Carol de Benito; Sebastià A. Bota; Jaume Segura 001 (PATMOS, 2006)

Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?. - Sebastià A. Bota; M. Rosales; José Luis Rosselló; Jaume Segura 001 (VTS, 2006)

Impact of Thermal Gradients on Clock Skew and Testing. - Sebastià A. Bota; José Luis Rosselló; Carol de Benito; Ali Keshavarzi; Jaume Segura 001 (IEEE Des. Test Comput., 2006)

Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. - José Luis Rosselló; Carol de Benito; Sebastià A. Bota; Jaume Segura 001 (DATE, 2007)

Using stochastic logic for efficient pattern recognition analysis. - José Luis Rosselló; Vincent Canals; Ivan de Paúl; Jaume Segura 001 (IJCNN, 2008)

A simple CMOS chaotic integrated circuit. - José Luis Rosselló; Vincent Canals; Ivan de Paúl; Sebastià A. Bota; Antoni Morro (IEICE Electron. Express, 2008)

Self-configuring spiking neural networks. - José Luis Rosselló; Ivan de Paúl; Vincent Canals (IEICE Electron. Express, 2008)

Spiking Neural Network Self-configuration for Temporal Pattern Recognition Analysis. - José Luis Rosselló; Ivan de Paúl; Vincent Canals; Antoni Morro (ICANN (1), 2009)

Practical Hardware Implementation of Self-configuring Neural Networks. - José Luis Rosselló; Vincent Canals; Antoni Morro; Ivan de Paúl (ISNN (3), 2009)

Chaos-Based Mixed Signal Implementation of Spiking Neurons. - José Luis Rosselló; Vincent Canals; Antoni Morro; Jaume Verd (Int. J. Neural Syst., 2009)

Hardware implementation of stochastic-based Neural Networks. - José Luis Rosselló; Vincent Canals; Antoni Morro (IJCNN, 2010)

Stochastic-based pattern-recognition analysis. - Vincent Canals; Antoni Morro; José Luis Rosselló (Pattern Recognit. Lett., 2010)

Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination. - Gabriel Torrens; Bartomeu Alorda; Salvador Barceló; José Luis Rosselló; Sebastià A. Bota; Jaume Segura 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Probabilistic-based neural network implementation. - José Luis Rosselló; Vincent Canals; Antoni Morro (IJCNN, 2012)

Hardware Implementation of Stochastic Spiking Neural Networks. - José Luis Rosselló; Vincent Canals; Antoni Morro; Antoni Oliver 002 (Int. J. Neural Syst., 2012)

Stochastic Spiking Neural Networks at the EDGE of CHAOS. - José Luis Rosselló; Vicent Canals; Antoni Oliver 002; Antoni Morro (IJCNN, 2014)

Low-cost hardware implementation of Reservoir Computers. - Miquel L. Alomar; Vicent Canals; Víctor Martínez-Moll; José Luis Rosselló (PATMOS, 2014)

Studying the Role of Synchronized and Chaotic Spiking Neural Ensembles in Neural Information Processing. - José Luis Rosselló; Vicent Canals; Antoni Oliver 002; Antoni Morro (Int. J. Neural Syst., 2014)

Stochastic-Based Implementation of Reservoir Computers. - Miquel L. Alomar; Vincent Canals; Víctor Martínez-Moll; José Luis Rosselló (IWANN (2), 2015)

Digital Implementation of a Single Dynamical Node Reservoir Computer. - Miquel L. Alomar; Miguel C. Soriano; Miguel Angel Escalona-Morán; Vincent Canals; Ingo Fischer; Claudio R. Mirasso; José Luis Rosselló (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Electrostatically actuated microbeam resonators as chaotic signal generators: A practical perspective. - Joan Barceló; José Luis Rosselló; Sebastià A. Bota; Jaume Segura 001; Jaume Verd (Commun. Nonlinear Sci. Numer. Simul., 2016)

A Stochastic Spiking Neural Network for Virtual Screening. - Antoni Morro; Vicent Canals; Antoni Oliver 002; Miquel L. Alomar; Fabio Galán-Prado; Pedro J. Ballester; José Luis Rosselló (IEEE Trans. Neural Networks Learn. Syst., 2018)