Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process. - Peter Hazucha; Tanay Kamik; Steven Walstra; Bradley A. Bloechel; James W. Tschanz; Jose Maiz; Krishnamurthy Soumyanath; Greg Dermer; Siva G. Narendra; Vivek De; Shekhar Borkar (CICC, 2003)

Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process. - Peter Hazucha; Tanay Karnik; Steven Walstra; Bradley A. Bloechel; James W. Tschanz; Jose Maiz; Krishnamurthy Soumyanath; Gregory E. Dermer; Siva G. Narendra; Vivek De; Shekhar Borkar (IEEE J. Solid State Circuits, 2004)