Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop. - José Manuel Cazeaux; Martin Omaña 001; Cecilia Metra (IOLTS, 2004)

New High Speed CMOS Self-Checking Voter. - José Manuel Cazeaux; Daniele Rossi 001; Cecilia Metra (IOLTS, 2004)

The Other Side of the Timing Equation: a Result of Clock Faults. - Cecilia Metra; Martin Omaña 001; Daniele Rossi 001; José Manuel Cazeaux; T. M. Mak (DFT, 2005)

On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. - José Manuel Cazeaux; Daniele Rossi 001; Martin Omaña 001; Cecilia Metra; Abhijit Chatterjee (IOLTS, 2005)

Self-Checking Voter for High Speed TMR Systems. - José Manuel Cazeaux; Daniele Rossi 001; Cecilia Metra (J. Electron. Test., 2005)

Novel on-chip circuit for jitter testing in high-speed PLLs. - José Manuel Cazeaux; Martin Omaña 001; Cecilia Metra (IEEE Trans. Instrum. Meas., 2005)

Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects. - Martin Omaña 001; José Manuel Cazeaux; Daniele Rossi 001; Cecilia Metra (DATE, 2006)

Can Clock Faults be Detected Through Functional Test? - Cecilia Metra; Daniele Rossi 001; Martin Omaña 001; José Manuel Cazeaux; T. M. Mak (DDECS, 2006)

Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. - Cecilia Metra; Martin Omaña 001; Daniele Rossi 001; José Manuel Cazeaux; T. M. Mak (IOLTS, 2006)

Fault tolerant techniques for electronic systems implemented by nanometer technology. - José Manuel Cazeaux (2006)

Accurate Linear Model for SET Critical Charge Estimation. - Daniele Rossi 001; José Manuel Cazeaux; Martin Omaña 001; Cecilia Metra; Abhijit Chatterjee (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Clock Faults Induced Min and Max Delay Violations. - Daniele Rossi 001; Martin Omaña 001; José Manuel Cazeaux; Cecilia Metra; T. M. Mak (J. Electron. Test., 2014)