Algebraic Support for Transformational Hardware Allocation. - José M. Mendías; Román Hermida; Milagros Fernández (ED&TC, 1996)

Formal Techniques for Hardware Allocation. - José M. Mendías; Román Hermida; Milagros Fernández (VLSI Design, 1997)

Correct High-Level Synthesis: a Formal Perspective. - José M. Mendías; Román Hermida (DATE, 1998)

A Unified Algorithm for Mutual Exclusiveness Identification. - Olga Peñalba; José M. Mendías; Román Hermida (EUROMICRO, 1999)

Execution Condition Analysis in High Level Synthesis: A Unified Approach. - Olga Peñalba; José M. Mendías; María C. Molina (ISSS, 2000)

High-level synthesis of multiple-precision circuitsindependent of data-objects length. - María C. Molina; José M. Mendías; Román Hermida (DAC, 2002)

Multiple-Precision Circuits Allocation Independent of Data-Objects Length. - María C. Molina; José M. Mendías; Román Hermida (DATE, 2002)

Maximizing Conditonal Reuse by Pre-Synthesis Transformations. - Olga Peñalba; José M. Mendías; Román Hermida (DATE, 2002)

Optimization of Equational Specifications Using Genetic Techniques. - Aitor Ibarra; José M. Mendías; Juan Lanchares; José Ignacio Hidalgo; Román Hermida (DSD, 2002)

Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis. - José M. Mendías; Román Hermida; María C. Molina; Olga Peñalba (DSD, 2002)

Bit-Level Allocation of Multiple-Precision Specifications. - María C. Molina; José M. Mendías; Román Hermida (DSD, 2002)

Source Code Transformation to Improve Conditional Hardware Reuse. - Olga Peñalba; José M. Mendías; Román Hermida (DSD, 2002)

Transformation of Equational Specification by Means of Genetic Programming. - Aitor Ibarra; Juan Lanchares; Jose Manuel Mendias; José Ignacio Hidalgo; Román Hermida (EuroGP, 2002)

Bit-level scheduling of heterogeneous behavioural specifications. - María C. Molina; José M. Mendías; Román Hermida (ICCAD, 2002)

A study about the efficiency of formal high-level synthesis applied to verification. - José M. Mendías; Román Hermida; Olga Peñalba (Integr., 2002)

A global approach to improve conditional hardware reuse in high-level synthesis. - Olga Peñalba; José M. Mendías; Román Hermida (J. Syst. Archit., 2002)

High-Level Allocation to Minimize Internal Hardware Wastage. - María C. Molina; José M. Mendías; Román Hermida (DATE, 2003)

Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level. - Marc Leeman; David Atienza; Francky Catthoor; Vincenzo De Florio; Geert Deconinck; Jose Manuel Mendias; Rudy Lauwereins (PATMOS, 2003)

Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis. - María C. Molina; Rafael Ruiz-Sautua; José M. Mendías; Román Hermida (PATMOS, 2003)

Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources. - María C. Molina; José M. Mendías; Román Hermida (J. Syst. Archit., 2003)

Garbage Collector Refinement for New Dynamic Multimedia Applications on Embedded Systems. - José Manuel Velasco; David Atienza; Francky Catthoor; Francisco Tirado; Katzalin Olcoz; Jose Manuel Mendias (Interaction between Compilers and Computer Architectures, 2004)

An integrated hardware/software approach for run-time scratchpad management. - Francesco Poletti; Paul Marchal; David Atienza; Luca Benini; Francky Catthoor; Jose Manuel Mendias (DAC, 2004)

Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications. - David Atienza; Stylianos Mamagkakis; Francky Catthoor; Jose Manuel Mendias; Dimitrios Soudris (DATE, 2004)

Behavioural Bitwise Scheduling Based on Computational Effort Balancing. - María C. Molina; Rafael Ruiz-Sautua; José M. Mendías; Román Hermida (DATE, 2004)

Reducing memory accesses with a system-level design methodology in customized dynamic memory management. - David Atienza; Stylianos Mamagkakis; Francky Catthoor; Jose Manuel Mendias; Dimitrios Soudris (ESTIMedia, 2004)

Fast prototyping and refinement of complex dynamic data types in multimedia applications for consumer embedded devices. - David Atienza; Marc Leeman; Francky Catthoor; Geert Deconinck; Jose Manuel Mendias; Vincenzo De Florio; Rudy Lauwereins (ICME, 2004)

Behavioural Scheduling to Balance the Bit-Level Computational Effort. - María C. Molina; Rafael Ruiz-Sautua; José M. Mendías; Román Hermida (ISVLSI, 2004)

Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems. - David Atienza; Stylianos Mamagkakis; Francky Catthoor; Jose Manuel Mendias; Dimitrios Soudris (PATMOS, 2004)

Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology. - Stylianos Mamagkakis; Alexandros Mpartzas; Georgios Pouiklis; David Atienza; Francky Catthoor; Dimitrios Soudris; Jose Manuel Mendias; Antonios Thanailakis (WWIC, 2004)

Memory-access-aware data structure transformations for embedded software with dynamic data accesses. - Edgar G. Daylight; David Atienza; Arnout Vandecappelle; Francky Catthoor; José M. Mendías (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Arrival time aware scheduling to minimize clock cycle length. - Rafael Ruiz-Sautua; María C. Molina; José M. Mendías; Román Hermida (ASP-DAC, 2005)

A Complete Network-On-Chip Emulation Framework. - Nicolas Genko; David Atienza; Giovanni De Micheli; Jose Manuel Mendias; Román Hermida; Francky Catthoor (DATE, 2005)

Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis. - Rafael Ruiz-Sautua; María C. Molina; José M. Mendías; Román Hermida (DATE, 2005)

Performance-driven read-after-write dependencies softening in high-level synthesis. - Rafael Ruiz-Sautua; María C. Molina; Jose Manuel Mendias; Román Hermida (ICCAD, 2005)

A novel approach for network on chip emulation. - Nicolas Genko; David Atienza; Giovanni De Micheli; Luca Benini; Jose Manuel Mendias; Román Hermida; Francky Catthoor (ISCAS (3), 2005)

Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs. - J. B. Pérez-Ramas; David Atienza; Miguel Peón-Quirós; Ivan Magan; Jose Manuel Mendias; Román Hermida (PARCO, 2005)

Energy Characterization of Garbage Collectors for Dynamic Applications on Embedded Systems. - José Manuel Velasco; David Atienza; Katzalin Olcoz; Francky Catthoor; Francisco Tirado; Jose Manuel Mendias (PATMOS, 2005)

Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications. - Stylianos Mamagkakis; Christos Baloukas; David Atienza; Francky Catthoor; Dimitrios Soudris; José M. Mendías; Antonios Thanailakis (WWIC, 2005)

Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications. - Marc Leeman; David Atienza; Geert Deconinck; Vincenzo De Florio; José M. Mendías; Chantal Ykman-Couvreur; Francky Catthoor; Rudy Lauwereins (J. VLSI Signal Process., 2005)

A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip. - David Atienza; Pablo García Del Valle; Giacomo Paci; Francesco Poletti; Luca Benini; Giovanni De Micheli; Jose Manuel Mendias (DAC, 2006)

Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems. - Stylianos Mamagkakis; David Atienza; Christophe Poucet; Francky Catthoor; Dimitrios Soudris; Jose Manuel Mendias (DATE, 2006)

Pre-synthesis optimization of multiplications to improve circuit performance. - Rafael Ruiz-Sautua; María C. Molina; José M. Mendías; Román Hermida (DATE, 2006)

Systematic design flow for dynamic data management in visual texture decoder of MPEG-4. - Alexandros Bartzas; Miguel Peón-Quirós; Stylianos Mamagkakis; David Atienza; Francky Catthoor; Dimitrios Soudris; Jose Manuel Mendias (ISCAS, 2006)

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework. - Pablo García Del Valle; David Atienza; Ivan Magan; Javier Garcia Flores; Esther Andres Perez; Jose Manuel Mendias; Luca Benini; Giovanni De Micheli (VLSI-SoC, 2006)

Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems. - David Atienza; Stylianos Mamagkakis; Francesco Poletti; Jose Manuel Mendias; Francky Catthoor; Luca Benini; Dimitrios Soudris (Integr., 2006)

Bitwise scheduling to balance the computational cost of behavioral specifications. - María C. Molina; Rafael Ruiz-Sautua; Jose Manuel Mendias; Román Hermida (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Systematic dynamic memory management design methodology for reduced memory footprint. - David Atienza; Jose Manuel Mendias; Stylianos Mamagkakis; Dimitrios Soudris; Francky Catthoor (ACM Trans. Design Autom. Electr. Syst., 2006)

Area optimization of multi-cycle operators in high-level synthesis. - María C. Molina; Rafael Ruiz-Sautua; Jose Manuel Mendias; Román Hermida (DATE, 2007)

Multi-processor operating system emulation framework with thermal feedback for systems-on-chip. - Salvatore Carta; Andrea Acquaviva; Pablo García Del Valle; David Atienza; Giovanni De Micheli; Fernando Rincón; Luca Benini; Jose Manuel Mendias (ACM Great Lakes Symposium on VLSI, 2007)

Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption. - Miguel Peón-Quirós; Alexandros Bartzas; Stylianos Mamagkakis; Francky Catthoor; Jose Manuel Mendias; Dimitrios Soudris (PATMOS, 2007)

Exploiting Bit-Level Delay Calculations to Soften Read-After-Write Dependences in Behavioral Synthesis. - Rafael Ruiz-Sautua; María C. Molina; Jose Manuel Mendias (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

HW-SW emulation framework for temperature-aware design in MPSoCs. - David Atienza; Pablo García Del Valle; Giacomo Paci; Francesco Poletti; Luca Benini; Giovanni De Micheli; Jose Manuel Mendias; Román Hermida (ACM Trans. Design Autom. Electr. Syst., 2007)

Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information. - Alexandros Bartzas; Miguel Peón-Quirós; Stylianos Mamagkakis; Francky Catthoor; Dimitrios Soudris; Jose Manuel Mendias (ASP-DAC, 2008)

Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis. - Alberto A. Del Barrio; María C. Molina; Jose Manuel Mendias; Esther Andres Perez; Román Hermida (DSD, 2008)

Applying speculation techniques to implement functional units. - Alberto A. Del Barrio; María C. Molina; Jose Manuel Mendias; Esther Andres Perez; Román Hermida; Francisco Tirado (ICCD, 2008)

Subword Switching Activity Minimization to Optimize Dynamic Power Consumption. - María C. Molina; Rafael Ruiz-Sautua; Alberto A. Del Barrio; Jose Manuel Mendias (IEEE Des. Test Comput., 2009)

Performance-driven scheduling of behavioural specifications. - María C. Molina; Rafael Ruiz-Sautua; Pedro Garcia-Repetto; José M. Mendías (Integr., 2009)

Direct memory access usage optimization in network applications for reduced memory latency and energy consumption. - Alexandros Bartzas; Miguel Peón-Quirós; Stylianos Mamagkakis; Francky Catthoor; Dimitrios Soudris; Jose Manuel Mendias (J. Embed. Comput., 2009)

Using Speculative Functional Units in high level synthesis. - Alberto A. Del Barrio; María C. Molina; Jose Manuel Mendias; Román Hermida; Seda Ogrenci Memik (DATE, 2010)

Software metadata: Systematic characterization of the memory behaviour of dynamic applications. - Alexandros Bartzas; Miguel Peón-Quirós; Christophe Poucet; Christos Baloukas; Stylianos Mamagkakis; Francky Catthoor; Dimitrios Soudris; Jose Manuel Mendias (J. Syst. Softw., 2010)

Power optimization in heterogenous datapaths. - Alberto A. Del Barrio; Seda Ogrenci Memik; María C. Molina; José M. Mendías; Román Hermida (DATE, 2011)

A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis. - Alberto A. Del Barrio; Seda Ogrenci Memik; María C. Molina; Jose Manuel Mendias; Román Hermida (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Multispeculative Addition Applied to Datapath Synthesis. - Alberto A. Del Barrio; Román Hermida; Seda Ogrenci Memik; José M. Mendías; María C. Molina (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Multispeculative additive trees in high-level synthesis. - Alberto A. Del Barrio; Román Hermida; Seda Ogrenci Memik; Jose Manuel Mendias; María C. Molina (DATE, 2013)

A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths. - Alberto A. Del Barrio; Seda Ogrenci Memik; María C. Molina; José M. Mendías; Román Hermida (Integr., 2013)

Improving circuit performance with multispeculative additive trees in high-level synthesis. - Alberto A. Del Barrio; Román Hermida; Seda Ogrenci Memik; Jose Manuel Mendias; María C. Molina (Microelectron. J., 2014)

Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems. - Miguel Peón-Quirós; Alexandros Bartzas; Stylianos Mamagkakis; Francky Catthoor; Jose Manuel Mendias; Dimitrios Soudris (ACM Trans. Embed. Comput. Syst., 2015)

Parametric Pipelined k-Means Implementation for Hyperspectral Processing on Spacecraft Embedded FPGA. - Borja Morcillo; Daniel Báscones; Carlos González 002; José M. Mendías; Daniel Mozos (IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2024)