A performance evaluation of the multiple bus network for multiprocessor systems. - Mateo Valero; José María Llabería; Jesús Labarta; Emilio Sanvicente; Tomás Lang (SIGMETRICS, 1983)

Analysis and Simulation of Multiplexed Single-Bus Networks With and Without Buffering. - José M. Llabería; Mateo Valero; Enrique Herrada Lillo; Jesús Labarta (ISCA, 1985)

Solving Matrix Problems with No Size Restriction on a Systolic Array Processor. - Juan J. Navarro; José M. Llabería; Mateo Valero (ICPP, 1986)

Computing Size-Independent Matrix Problems on Systolic Array Processors. - Juan J. Navarro; José M. Llabería; Mateo Valero (ISCA, 1986)

Partitioning: An Essential Step in Mapping Algorithms Into Systolic Array Processors. - Juan J. Navarro; José M. Llabería; Mateo Valero (Computer, 1987)

A mechanism for reducing the cost of branches in RISC architectures. - Antonio González 001; José María Llabería; Jordi Cortadella (Microprocess. Microprogramming, 1988)

Instruction fetch unit for parallel execution of branch instructions. - Antonio González 001; José M. Llabería (ICS, 1989)

Systematic Hardware Adaptation of Systolic Algorithms. - Miguel Valero-García; Juan J. Navarro; José M. Llabería; Mateo Valero (ISCA, 1989)

Implementation of systolic algorithms using pipelined functional units. - Miguel Valero-García; Juan J. Navarro; José M. Llabería; Mateo Valero (ASAP, 1990)

Transformation of systolic algorithms for interleaving partitions. - Agustín Fernández; José M. Llabería; Juan J. Navarro; Miguel Valero-García (ASAP, 1991)

Interleaving Partitions of Systolic Algorithms for Programming Distributed Memory Multiprocessors. - Agustín Fernández; José M. Llabería; Juan J. Navarro; Miguel Valero-García (EDMCC, 1991)

On Automatic Loop Data-Mapping for Distributed-Memory Multiprocessors. - Jordi Torres; Eduard Ayguadé; Jesús Labarta; José M. Llabería; Mateo Valero (EDMCC, 1991)

Balanced Loop Partitioning Using GTS. - Jesús Labarta; Eduard Ayguadé; Jordi Torres; Mateo Valero; José M. Llabería (LCPC, 1991)

Performance evaluation of transputer systems with linear algebra problems. - Agustín Fernández; José María Llabería; Juan J. Navarro; Miguel Valero-García (Microprocessing and Microprogramming, 1991)

Conflict-Free Strides for Vectors in Matched Memories. - Mateo Valero; Tomás Lang; José María Llabería; Montse Peiron; Juan J. Navarro; Eduard Ayguadé (Parallel Process. Lett., 1991)

Scheduling partitions in systolic algorithms. - Alvaro Suárez; José M. Llabería; Agustín Fernández (ASAP, 1992)

Increasing the Number of Strides for Conflict-Free Vector Access. - Mateo Valero; Tomás Lang; José M. Llabería; Montse Peiron; Eduard Ayguadé; Juan J. Navarro (ISCA, 1992)

Evaluation of A + B = K Conditions Without Carry Propagation. - Jordi Cortadella; José M. Llabería (IEEE Trans. Computers, 1992)

A method for implementation of one-dimensional systolic algorithms with data contraflow using pipelined functional units. - Miguel Valero-García; Juan J. Navarro; José María Llabería; Mateo Valero; Tomás Lang (J. VLSI Signal Process., 1992)

Reducing Branch Delay to Zero in Pipelined Processors. - Antonio González 001; José M. Llabería (IEEE Trans. Computers, 1993)

Out-of-order access to vector elements in order to reduce conflicts in vector processors. - Anna M. del Corral; José M. Llabería (SPDP, 1994)

Access order to avoid inter-vector-conflicts in complex memory systems. - Anna M. del Corral; José M. Llabería (IPPS, 1995)

Loop Transformation Using Nonunimodular Matrices. - Agustín Fernández; José M. Llabería; Miguel Valero-García (IEEE Trans. Parallel Distributed Syst., 1995)

Increasing the Effective Memory Bandwidth in Multivector Processors. - Anna M. del Corral; José M. Llabería (EUROMICRO, 1996)

A Unified Transformation Technique for Multilevel Blocking. - Marta Jiménez; José M. Llabería; Agustín Fernández; Enric Morancho (Euro-Par, Vol. I, 1996)

Reducing Inter-Vector-Conflicts in Complex Memory Systems. - Anna M. del Corral; José M. Llabería (International Conference on Supercomputing, 1996)

Increasing the Effective Bandwidth of Complex Memory Systems in Multivector Processors. - Anna M. del Corral; José María Llabería (SC, 1996)

Split Last-Address Predictor. - Enric Morancho; José M. Llabería; Àngel Olivé (IEEE PACT, 1998)

Performance Evaluation of Tiling for the Register Level. - Marta Jiménez; José M. Llabería; Agustín Fernández (HPCA, 1998)

A General Algorithm for Tiling the Register Level. - Marta Jiménez; José M. Llabería; Agustín Fernández; Enric Morancho (International Conference on Supercomputing, 1998)

Loop bounds computation for multilevel tiling. - Marta Jiménez; José María Llabería; Agustín Fernández (PDP, 1998)

New Access Order to Reduce Inter-Vector-Conflicts. - Anna M. del Corral; José M. Llabería (VECPAR, 1998)

Looking at History to Filter Allocations in Prediction Tables. - Enric Morancho; José M. Llabería; Àngel Olivé (IEEE PACT, 1999)

Minimizing Conflicts Between Vector Streams in Interleaved Memory Systems. - Anna M. del Corral; José M. Llabería (IEEE Trans. Computers, 1999)

Two-Level Address Storage and Address Prediction (Research Note). - Enric Morancho; José M. Llabería; Àngel Olivé (Euro-Par, 2000)

On the Performance of Hand vs. Automatically Optimized Numerical Codes. - Marta Jiménez; José M. Llabería; Agustín Fernández (HPCA, 2000)

Modeling load address behaviour through recurrences. - Luis M. Ramos; Pablo E. Ibáñez 001; Víctor Viñals; José M. Llabería (ISPASS, 2000)

Recovery Mechanism for Latency Misprediction. - Enric Morancho; José María Llabería; Àngel Olivé (IEEE PACT, 2001)

Register tiling in nonrectangular iteration spaces. - Marta Jiménez; José M. Llabería; Agustín Fernández (ACM Trans. Program. Lang. Syst., 2002)

Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation. - María Jesús Garzarán; Milos Prvulovic; Víctor Viñals; José María Llabería; Lawrence Rauchwerger; Josep Torrellas (IEEE PACT, 2003)

Counteracting Bank Misprediction in Sliced First-Level Caches. - Enrique F. Torres; Pablo Ibáñez 001; Víctor Viñals; José María Llabería (Euro-Par, 2003)

Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors. - María Jesús Garzarán; Milos Prvulovic; José María Llabería; Víctor Viñals; Lawrence Rauchwerger; Josep Torrellas (HPCA, 2003)

A Cost-Effective Implementation of Multilevel Tiling. - Marta Jiménez; José M. Llabería; Agustín Fernández (IEEE Trans. Parallel Distributed Syst., 2003)

A Mechanism for Verifying Data Speculation. - Enric Morancho; José María Llabería; Àngel Olivé (Euro-Par, 2004)

Contents Management in First-Level Multibanked Data Caches. - Enrique F. Torres; Pablo Ibáñez 001; Víctor Viñals; José María Llabería (Euro-Par, 2004)

Store Buffer Design in First-Level Multibanked Data Caches. - Enrique F. Torres; Pablo Ibáñez 001; Víctor Viñals; José María Llabería (ISCA, 2005)

Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors. - María Jesús Garzarán; Milos Prvulovic; José María Llabería; Víctor Viñals; Lawrence Rauchwerger; Josep Torrellas (ACM Trans. Archit. Code Optim., 2005)

Speeding-Up Synchronizations in DSM Multiprocessors. - Agustín De Dios Hernández; Benjamín Sahelices Fernández; Pablo Ibáñez 001; Víctor Viñals; José M. Llabería (Euro-Par, 2006)

An Enhancement for a Scheduling Logic Pipelined over two Cycles . - Ruben Gran Tejero; Enric Morancho; Àngel Olivé; José María Llabería (ICCD, 2006)

On reducing energy-consumption by late-inserting instructions into the issue queue. - Enric Morancho; José María Llabería; Àngel Olivé (ISLPED, 2007)

Characterization of Apache web server with Specweb2005. - Ana Bosque; Pablo Ibáñez 001; Víctor Viñals; Per Stenström; José María Llabería (MEDEA@PACT, 2007)

A comparison of two policies for issuing instructions speculatively. - Enric Morancho; José María Llabería; Àngel Olivé (J. Syst. Archit., 2007)

A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors. - Benjamín Sahelices; Pablo Ibáñez 001; Víctor Viñals; José María Llabería (Euro-Par, 2009)

On reducing misspeculations in a pipelined scheduler. - Ruben Gran Tejero; Enric Morancho; Àngel Olivé; José María Llabería (IPDPS, 2009)

Store Buffer Design for Multibanked Data Caches. - Enrique F. Torres; Pablo Ibáñez 001; Víctor Viñals Yúfera; José María Llabería (IEEE Trans. Computers, 2009)

Filtering Directory Lookups in CMPs with Write-Through Caches. - Ana Bosque; Víctor Viñals; Pablo Ibáñez 001; José María Llabería (Euro-Par (1), 2011)

Filtering directory lookups in CMPs. - Ana Bosque; Víctor Viñals; Pablo Ibáñez 001; José M. Llabería (Microprocess. Microsystems, 2011)

Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers. - Benjamín Sahelices; Agustín De Dios Hernández; Pablo Ibáñez 001; Víctor Viñals Yúfera; José María Llabería (J. Comput. Sci. Technol., 2012)

ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache. - Jorge Albericio; Ruben Gran Tejero; Pablo Ibáñez 001; Víctor Viñals; José María Llabería (ACM Trans. Archit. Code Optim., 2012)

The reuse cache: downsizing the shared last-level cache. - Jorge Albericio; Pablo Ibáñez 001; Víctor Viñals; José M. Llabería (MICRO, 2013)

Exploiting reuse locality on inclusive shared last-level caches. - Jorge Albericio; Pablo Ibáñez 001; Víctor Viñals; José María Llabería (ACM Trans. Archit. Code Optim., 2013)

Reuse Detector: Improving the Management of STT-RAM SLLCs. - Roberto Rodríguez-Rodríguez; Javier Díaz; Fernando Castro; Pablo Ibáñez 001; Daniel Chaver; Víctor Viñals; Juan Carlos Saez; Manuel Prieto-Matías; Luis Piñuel; Teresa Monreal Arnal; José María Llabería (Comput. J., 2018)

ReD: A reuse detector for content selection in exclusive shared last-level caches. - Javier Díaz; Teresa Monreal; Pablo Ibáñez 001; José M. Llabería; Víctor Viñals (J. Parallel Distributed Comput., 2019)

Near-optimal replacement policies for shared caches in multicore processors. - Javier Díaz; Pablo Ibáñez 001; Teresa Monreal; Víctor Viñals; José M. Llabería (J. Supercomput., 2021)

Forecasting lifetime and performance of a novel NVM last-level cache with compression. - Carlos Escuin; Pablo Ibáñez 001; Teresa Monreal; José M. Llabería; Víctor Viñals (CoRR, 2022)

L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime. - Carlos Escuin; Pablo Ibáñez 001; Teresa Monreal; José M. Llabería; Víctor Viñals (CoRR, 2022)

MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array. - Carlos Escuin; Fernando García-Redondo; Mahdi Zahedi; Pablo Ibáñez 001; Teresa Monreal; Víctor Viñals; José María Llabería; James Myers; Julien Ryckaert; Dwaipayan Biswas; Francky Catthoor (ICECS, 2023)