Retiming sequential circuits for low power. - José Monteiro 001; Srinivas Devadas; Abhijit Ghosh (ICCAD, 1993)

A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits. - José Monteiro 001; Srinivas Devadas; Bill Lin 001 (DAC, 1994)

Bitwise Encoding of Finite State Machines. - José Monteiro 001; James H. Kukula; Srinivas Devadas; Horácio C. Neto (VLSI Design, 1994)

Precomputation-based sequential logic optimization for low power. - Mazhar Alidina; José Monteiro 001; Srinivas Devadas; Abhijit Ghosh; Marios C. Papaefthymiou (IEEE Trans. Very Large Scale Integr. Syst., 1994)

Optimization of combinational and sequential logic circuits for low power using precomputation. - José Monteiro 001; John Rinderknecht; Srinivas Devadas; Abhijit Ghosh (ARVLSI, 1995)

Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs. - José Monteiro 001; Srinivas Devadas (ISLPD, 1995)

Power estimation methods for sequential logic circuits. - Chi-Ying Tsui; José Monteiro 001; Massoud Pedram; Srinivas Devadas; Alvin M. Despain; Bill Lin 001 (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Scheduling Techniques to Enable Power Management. - José Monteiro 001; Srinivas Devadas; Pranav Ashar; Ashutosh Mauskar (DAC, 1996)

Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. - Chi-Ying Tsui; José Monteiro 001; Massoud Pedram; Srinivas Devadas; Alvin M. Despain; Bill Lin 001 (IEEE Trans. Very Large Scale Integr. Syst., 1996)

Techniques for power estimation and optimization at the logic level: A survey. - José Monteiro 001; Srinivas Devadas (J. VLSI Signal Process., 1996)

A computer-aided design methodology for low power circuits. - José Carlos Alves Pereira Monteiro (1996)

Switching activity estimation using limited depth reconvergent path analysis. - José C. Costa; José C. Monteiro 001; Srinivas Devadas (ISLPED, 1997)

Estimation of average switching activity in combinational logic circuits using symbolic simulation. - José Monteiro 001; Srinivas Devadas; Abhijit Ghosh; Kurt Keutzer; Jacob K. White 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Finite State Machine Decomposition For Low Power. - José C. Monteiro 001; Arlindo L. Oliveira (DAC, 1998)

Techniques for power management at the logic level. - José C. Monteiro 001 (ICECS, 1998)

Hardware support for CAN fault-tolerant communication. - José Rufino; Nuno Pedrosa; José Monteiro 001; Paulo Veríssimo; Guilherme Arroz (ICECS, 1998)

Power Estimation Under User-Specified Input Sequences and Programs. - José Monteiro 001; Srinivas Devadas (Integr. Comput. Aided Eng., 1998)

Sequential logic optimization for low power using input-disabling precomputation architectures. - José Monteiro 001; Srinivas Devadas; Abhijit Ghosh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

A probabilistic approach for RT-level power modeling. - José C. Costa; José Monteiro 001; L. Miguel Silveira; Srinivas Devadas (ICECS, 1999)

Integrating Dynamic Power Management in the Design Flow. - Antônio Mota; Nuno Ferreira; Arlindo L. Oliveira; José Monteiro 001 (VLSI, 1999)

CAD Techniques for Embedded System Design. - Srinivas Devadas; Sharad Malik; José Monteiro 001; Luciano Lavagno (VLSI Design, 1999)

Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation. - Paulo F. Flores; José C. Costa; Horácio C. Neto; José Monteiro 001; João Marques-Silva 001 (VLSI Design, 1999)

FSM decomposition by direct circuit manipulation applied to low power design. - José C. Monteiro 001; Arlindo L. Oliveira (ASP-DAC, 2000)

Observability Analysis of Embedded Software for Coverage-Directed Validation. - José C. Costa; Srinivas Devadas; José Monteiro 001 (ICCAD, 2000)

Probabilistic Bottom-Up RTL Power Estimation. - Ricardo Ferreira; Anne-Marie Trullemans; José C. Costa; José Monteiro 001 (ISQED, 2000)

Power Efficient Arithmetic Operand Encoding. - Eduardo Costa 001; Sergio Bampi; José Monteiro 001 (SBCCI, 2001)

Power Optimized Viterbi Decoder Implementation through Architectural Transforms. - João Portela; José Monteiro 001 (SBCCI, 2001)

A New Architecture for Signed Radix-2m Pure Array Multipliers. - Eduardo A. C. da Costa; Sergio Bampi; José Monteiro 001 (ICCD, 2002)

A New Architecture for 2's Complement Gray Encoded Array Multiplier. - Eduardo Costa 001; Sergio Bampi; José Monteiro 001 (SBCCI, 2002)

Implicit FSM decomposition applied to low-power design. - José C. Monteiro 001; Arlindo L. Oliveira (IEEE Trans. Very Large Scale Integr. Syst., 2002)

A New Pipelined Array Architecture for Signed Multiplication. - Eduardo A. C. da Costa; Sergio Bampi; José Monteiro 001 (SBCCI, 2003)

Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths. - Eduardo A. C. da Costa; José C. Monteiro 001; Sergio Bampi (VLSI-SoC (Selected Papers), 2003)

An improved synthesis method for low power hardwired FIR filters. - Vagner S. Rosa; Eduardo A. C. da Costa; José C. Monteiro 001; Sergio Bampi (SBCCI, 2004)

Power Estimation Using Probability Polynomials. - José C. Costa; Luís Miguel Silveira; Srinivas Devadas; José Monteiro 001 (Des. Autom. Embed. Syst., 2004)

Maximal sharing of partial terms in MCM under minimal signed digit representation. - Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (ECCTD, 2005)

An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications. - Paulo F. Flores; José Monteiro 001; Eduardo A. C. da Costa (ICCAD, 2005)

Design of a radix-2m hybrid array multiplier using carry save adder format. - Mateus Fonseca; Eduardo A. C. da Costa; Sergio Bampi; José Monteiro 001 (SBCCI, 2005)

A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures. - Leonardo Londero de Oliveira; Cristiano Santos; Daniel Lima Ferrão; Eduardo A. C. da Costa; José Monteiro 001; João Baptista dos Santos Martins; Sergio Bampi; Ricardo Augusto da Luz Reis (VLSI-SoC, 2005)

Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (DAC, 2006)

ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ICECS, 2006)

Exploiting general coefficient representation for the optimal sharing of partial products in MCMs. - Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (SBCCI, 2006)

Optimization of Area in Digital FIR Filters using Gate-Level Metrics. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (DAC, 2007)

Minimum number of operations under a general number representation for digital filter synthesis. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (ECCTD, 2007)

Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications. - Levent Aksoy; Ece Olcay Günes; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (SiPS, 2007)

A new array architecture for signed multiplication using Gray encoded radix-2m operands. - Eduardo A. C. da Costa; José Monteiro 001; Sergio Bampi (Integr., 2007)

Generating Worst-Case Stimuli for Accurate Power Grid Analysis. - Pedro Marques Morgado; Paulo F. Flores; José C. Monteiro 001; Luís Miguel Silveira (PATMOS, 2008)

Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A MILP-based approach to path sensitization of embedded software. - José C. Costa; José C. Monteiro 001 (DATE, 2009)

Parameter tuning in SVM-based power macro-modeling. - António Gusmão; L. Miguel Silveira; José Monteiro 001 (ISQED, 2009)

Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates. - Sidinei Ghissoni; João Baptista dos Santos Martins; Ricardo Augusto da Luz Reis; José C. Monteiro 001 (PATMOS, 2009)

Power Macro-Modeling Using an Iterative LS-SVM Method. - António Gusmão; Luís Miguel Silveira; José Monteiro 001 (VLSI-SoC, 2009)

A new quaternary FPGA based on a voltage-mode multi-valued circuit. - Cristiano Lazzari; Paulo F. Flores; José Monteiro 001; Luigi Carro (DATE, 2010)

Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (DSD, 2010)

Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach. - Sidinei Ghissoni; Eduardo Costa 001; Cristiano Lazzari; José Monteiro 001; Levent Aksoy; Ricardo Reis 001 (ICECS, 2010)

Voltage-mode quaternary FPGAs: An evaluation of interconnections. - Cristiano Lazzari; Paulo F. Flores; José Monteiro 001; Luigi Carro (ISCAS, 2010)

An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs. - Cristiano Lazzari; Jorge R. Fernandes; Paulo F. Flores; José Monteiro 001 (PATMOS, 2010)

CentroidM: a centroid-based localization algorithm for mobile sensor networks. - Leonardo Londero de Oliveira; João Baptista dos Santos Martins; Gustavo Fernando Dessbesell; José Monteiro 001 (SBCCI, 2010)

Design of low-complexity and high-speed digital Finite Impulse Response filters. - Diego Jaccottet; Eduardo Costa 001; Levent Aksoy; Paulo F. Flores; José Monteiro 001 (VLSI-SoC, 2010)

Optimally Solving the MCM Problem Using Pseudo-Boolean Satisfiability - Nuno P. Lopes; Levent Aksoy; Vasco Manquinho; José Monteiro 001 (CoRR, 2010)

Efficient Dedicated Multiplication Blocks for 2's Complement Radix-2m Array Multipliers. - Leandro Zafalon Pieper; Eduardo A. C. da Costa; Sérgio J. M. de Almeida; Sergio Bampi; José C. Monteiro 001 (J. Comput., 2010)

Optimization of gate-level area in high throughput Multiple Constant Multiplications. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ECCTD, 2011)

Design of low-power multiple constant multiplications using low-complexity minimum depth operations. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ACM Great Lakes Symposium on VLSI, 2011)

Efficient shift-adds design of digit-serial multiple constant multiplications. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ACM Great Lakes Symposium on VLSI, 2011)

Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization. - Sidinei Ghissoni; Eduardo Costa 001; José Monteiro 001; Ricardo Reis 001 (ICECS, 2011)

Optimization of area in digit-serial Multiple Constant Multiplications at gate-level. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ISCAS, 2011)

Hardware implementation of a centroid-based localization algorithm for mobile sensor networks. - Leonardo L. de Oliveira; Gustavo Fernando Dessbesell; João B. Martins; José Monteiro 001 (ISCAS, 2011)

A hybrid algorithm for the optimization of area and delay in linear DSP transforms. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (VLSI-SoC, 2011)

Multiplierless Design of Linear DSP Transforms. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (VLSI-SoC (Selected Papers), 2011)

Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays. - Cristiano Lazzari; Jorge R. Fernandes; Paulo F. Flores; José Monteiro 001 (J. Low Power Electron., 2011)

Finding the optimal tradeoff between area and delay in multiple constant multiplications. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (Microprocess. Microsystems, 2011)

Design of low-complexity digital finite impulse response filters on FPGAs. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (DATE, 2012)

Multiple tunable constant multiplications: Algorithms and applications. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ICCAD, 2012)

Design and characterization of a QLUT in a standard CMOS process. - Diogo Brito; Jorge R. Fernandes; Paulo F. Flores; José Monteiro 001 (ICECS, 2012)

Efficient area and power multiplication part of FFT based on twiddle factor decomposition. - Sidinei Ghissoni; Eduardo Costa 001; José Monteiro 001; Ricardo Reis 001 (ICECS, 2012)

Hardware pipelining of runtime-detected loops. - João Bispo; João M. P. Cardoso; José Monteiro 001 (SBCCI, 2012)

High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (Integr., 2012)

Optimization Algorithms for the Multiplierless Realization of Linear Transforms. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ACM Trans. Design Autom. Electr. Syst., 2012)

Exploration of tradeoffs in the design of integer cosine transforms for image compression. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ECCTD, 2013)

SIREN: a depth-first search algorithm for the filter design optimization problem. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (ACM Great Lakes Symposium on VLSI, 2013)

Standard CMOS voltage-mode QLUT using a clock boosting technique. - Diogo Brito; Jorge R. Fernandes; Paulo F. Flores; José Monteiro 001 (NEWCAS, 2013)

Combination of radix-2m multiplier blocks and adder compressors for the design of efficient 2's complement 64-bit array multipliers. - Leandro Zafalon Pieper; Eduardo A. C. da Costa; José C. Monteiro 001 (SBCCI, 2013)

Automatic Equivalence Checking of UF+IA Programs. - Nuno P. Lopes; José Monteiro 001 (SPIN, 2013)

Towards the least complex time-multiplexed constant multiplication. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (VLSI-SoC, 2013)

Coverage-directed observability-based validation for embedded software. - José C. Costa; José C. Monteiro 001 (ACM Trans. Design Autom. Electr. Syst., 2013)

Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Optimization of design complexity in time-multiplexed constant multiplications. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (DATE, 2014)

Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (ICCD, 2014)

ECHO: A novel method for the multiplierless design of constant array vector multiplication. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (ISCAS, 2014)

Weakest Precondition Synthesis for Compiler Optimizations. - Nuno P. Lopes; José Monteiro 001 (VMCAI, 2014)

A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (Circuits Syst. Signal Process., 2014)

Multiplierless Design of Folded DSP Blocks. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (ACM Trans. Design Autom. Electr. Syst., 2014)

Approximation of multiple constant multiplications using minimum look-up tables on FPGA. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (ISCAS, 2015)

Exact and Approximate Algorithms for the Filter Design Optimization Problem. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (IEEE Trans. Signal Process., 2015)

Quaternary Logic Lookup Table in Standard CMOS. - Diogo Brito; Taimur Gibran Rabuske; Jorge R. Fernandes; Paulo F. Flores; José Monteiro 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A novel method for the approximation of multiplierless constant matrix vector multiplication. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (EURASIP J. Embed. Syst., 2016)

Automatic equivalence checking of programs with uninterpreted functions and integer arithmetic. - Nuno P. Lopes; José Monteiro 001 (Int. J. Softw. Tools Technol. Transf., 2016)

Analysis of short-circuit conditions in logic circuits. - João Afonso; José Monteiro 001 (DATE, 2017)

A variable RADIX-2r algorithm for single constant multiplication. - Ahmed Liacha; Abdelkrim Kamel Oudjida; Farid Ferguene; José Monteiro 001; Paulo F. Flores (NEWCAS, 2017)

Computer Architecture - Digital Circuits to Microprocessors - Guilherme Arroz; José Monteiro 001; Arlindo L. Oliveira (Computer Architecture, 2018)

Short-circuit Analysis using a Parallel QBF Solver. - Rafael Santos; João Afonso; José Monteiro 001 (DCIS, 2020)

A highly parallel algorithm for computing the action of a matrix exponential on a vector based on a multilevel Monte Carlo method. - Juan A. Acebrón; José R. Herrero 001; José Monteiro 001 (Comput. Math. Appl., 2020)

Radix-2 r recoding with common subexpression elimination for multiple constant multiplication. - Ahmed Liacha; Abdelkrim Kamel Oudjida; Mohammed Bakiri; José Monteiro 001; Paulo F. Flores (IET Circuits Devices Syst., 2020)

Particle-In-Cell Simulation Using Asynchronous Tasking. - Nicolas L. Guidotti; Pedro Ceyrat; João Barreto 001; José Monteiro 001; Rodrigo Rodrigues 001; Ricardo Fonseca; Xavier Martorell; Antonio J. Peña (Euro-Par, 2021)

Efficient and Eventually Consistent Collective Operations. - Roman Iakymchuk; Amândio Faustino; Andrew P. J. Emerson; João Barreto 001; Valeria Bartsch; Rodrigo Rodrigues 001; José C. Monteiro 001 (IPDPS Workshops, 2021)

Dynamic Page Placement on Real Persistent Memory Systems. - Miguel Marques; Ilia Kuzmin; João Barreto 001; José Monteiro 001; Rodrigo Rodrigues 001 (CoRR, 2021)

Towards OmpSs-2 and OpenACC interoperation. - Orestis Korakitis; Simon Garcia De Gonzalo; Nicolas L. Guidotti; João Pedro Barreto 002; José C. Monteiro 001; Antonio J. Peña (PPoPP, 2022)

OmpSs-2 and OpenACC Interoperation. - Orestis Korakitis; Simon Garcia de Gonzalo; Nicolas L. Guidotti; João Barreto 001; José Monteiro 001; Antonio J. Peña (WACCPD@SC, 2022)

A distributed Monte Carlo based linear algebra solver applied to the analysis of large complex networks. - Filipe Magalhães; José Monteiro 001; Juan A. Acebrón; José R. Herrero 001 (Future Gener. Comput. Syst., 2022)

A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective. - Helena Cruz; Mário P. Véstias; José Monteiro 001; Horácio C. Neto; Rui Policarpo Duarte (Remote. Sens., 2022)

Mobile Localization Techniques for Wireless Sensor Networks: Survey and Recommendations. - Leonardo L. de Oliveira; Gabriel H. Eisenkraemer; Everton Alceu Carara; João B. Martins; José Monteiro 001 (ACM Trans. Sens. Networks, 2023)

A stochastic method for solving time-fractional differential equations. - Nicolas L. Guidotti; Juan A. Acebrón; José Monteiro 001 (Comput. Math. Appl., 2024)

Parallelization Strategies for the Randomized Kaczmarz Algorithm on Large-Scale Dense Systems. - Inês A. Ferreira; Juan A. Acebrón; José Monteiro 001 (CoRR, 2024)

A Fast Monte Carlo Algorithm for Evaluating Matrix Functions with Application in Complex Networks. - Nicolas L. Guidotti; Juan A. Acebrón; José Monteiro 001 (J. Sci. Comput., 2024)

Correction to: A Fast Monte Carlo Algorithm for Evaluating Matrix Functions with Application in Complex Networks. - Nicolas L. Guidotti; Juan A. Acebrón; José Monteiro 001 (J. Sci. Comput., 2025)

Accelerating a restarted Krylov method for matrix functions with randomization. - Nicolas L. Guidotti; Per-Gunnar Martinsson; Juan A. Acebrón; José Monteiro 001 (CoRR, 2025)

Survey of a class of iterative row-action methods: The Kaczmarz method. - Inês A. Ferreira; Juan A. Acebrón; José Monteiro 001 (Numer. Algorithms, 2025)