José Neves

According to our database, José Neves authored at least 25 papers between 1994 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

IBM z14 design methodology enhancements in the 14-nm technology node.

Christopher J. Berry, James D. Warnock, John Badar, Dean G. Bair, Erwin Behnen, Brian Bell, Alper Buyuktosunoglu, Chris Cavitt, Pierce Chuang, Ofer Geva, Dina Hamid, John Isakson, Preetham Lobo, Frank Malgioglio, Guenter Mayer, José Luis Neves, Thomas Strach, Jesse Surprise, Christos Vezyrtzis, Tobias Webel, David Wolpert

IBM J. Res. Dev., 2018

IBM z14™: 14nm microprocessor for the next-generation mainframe.

Christopher J. Berry, James D. Warnock, John Isakson, John Badar, Brian Bell, Frank Malgioglio, Guenter Mayer, Dina Hamid, Jesse Surprise, David Wolpert, Ofer Geva, Bill Huott, Leon J. Sigal, Sean M. Carey, Richard F. Rizzolo, Ricardo Nigaglioni, Mark Cichanowski, Dureseti Chidambarrao, Christian Jacobi, Anthony Saporito, Arthur O'neill, Robert J. Sonnelitter, Christian G. Zoellin, Michael H. Wood, José Neves

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2015

IBM z13 circuit design and methodology.

James D. Warnock, Christopher J. Berry, Michael H. Wood, Leon J. Sigal, Yun-Chan Myung, Guenter Mayer, Mark D. Mayo, Y. Chan, Frank Malgioglio, Gerald Strevig, Charudhattan Nagarajan, Sean M. Carey, Gerard Salem, Friedrich Schroeder, Howard H. Smith, Di Phan, Ricardo Nigaglioni, Thomas Strach, Matthew M. Ziegler, Niels Fricke, K. Lind, José Neves, Sridhar H. Rangarajan, J. P. Surprise, John Isakson, John Badar, Doug Malone, Donald W. Plass, A. Aipperspach, Dieter F. Wendel, Robert M. Averill III, Ruchir Puri

IBM J. Res. Dev., 2015

2012

Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System.

James D. Warnock, Yiu-Hing Chan, Sean M. Carey, Huajun Wen, Patrick J. Meaney, Guenter Gerwig, Howard H. Smith, Yuen H. Chan, John Davis, Paul Bunce, Antonio Pelella, Daniel Rodko, Pradip Patel, Thomas Strach, Doug Malone, Frank Malgioglio, José Neves, David L. Rude, William V. Huott

IEEE J. Solid State Circuits, 2012

2006

Parallelizing post-placement timing optimization.

Jiyoun Kim, Marios C. Papaefthymiou, José Luis Neves

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

2005

Multi-Session Partitioning for Parallel Timing Optimization.

Jiyoun Kim, José Neves, Marios C. Papaefthymiou

Proceedings of the Sixth International Conference on Parallel and Distributed Computing, 2005

2002

Inductance Effects in RLC Trees.

Yehea I. Ismail, Eby G. Friedman, José Luis Neves

J. Circuits Syst. Comput., 2002

2001

Exploiting the on-chip inductance in high-speed clock distribution networks.

Yehea I. Ismail, Eby G. Friedman, José Luis Neves

IEEE Trans. Very Large Scale Integr. Syst., 2001

Steiner tree optimization for buffers, blockages, and bays.

Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

2000

Equivalent Elmore delay for RLC trees.

Yehea I. Ismail, Eby G. Friedman, José Luis Neves

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Buffer Library Selection.

José Luis Neves, Stephen T. Quay

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999

Figures of merit to characterize the importance of on-chip inductance.

Yehea I. Ismail, Eby G. Friedman, José Luis Neves

IEEE Trans. Very Large Scale Integr. Syst., 1999

Signal waveform characterization in RLC trees.

Yehea I. Ismail, Eby G. Friedman, José Luis Neves

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Repeater insertion in tree structured inductive interconnect.

Yehea I. Ismail, Eby G. Friedman, José Luis Neves

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Equivalent Elmore Delay for <i>RLC</i> Trees.

Yehea I. Ismail, Eby G. Friedman, José Luis Neves

Proceedings of the 36th Conference on Design Automation, 1999

1998

Automated Synthesis of Skew-Based Clock Distribution Networks.

José Luis Neves, Eby G. Friedman

VLSI Design, 1998

Power dissipated by CMOS gates driving lossless transmission lines.

Yehea I. Ismail, Eby G. Friedman, José Luis Neves

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Transient power in CMOS gates driving LC transmission lines.

Yehea I. Ismail, Eby G. Friedman, José Luis Neves

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

Methods for calculating coupling noise in early design: a comparative analysis.

Khalid Rahmat, José Neves, Jin-Fuw Lee

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines.

Yehea I. Ismail, Eby G. Friedman, José Luis Neves

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997

Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations.

José Luis Neves, Eby G. Friedman

J. VLSI Signal Process., 1997

1996

Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew.

José Luis Neves, Eby G. Friedman

IEEE Trans. Very Large Scale Integr. Syst., 1996

Optimal Clock Skew Scheduling Tolerant to Process Variations.

José Luis Neves, Eby G. Friedman

Proceedings of the 33st Conference on Design Automation, 1996

1995

Minimizing Power Dissipation in Non-Zero Skew-Based Clock Distribution Networks.

José Luis Neves, Eby G. Friedman

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994

Circuit Synthesis of Clock Distribution Networks Based on Non-Zero Clock Skew.

José Luis Neves, Eby G. Friedman

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994