Circuit Synthesis of Clock Distribution Networks Based on Non-Zero Clock Skew. - José Luis Neves; Eby G. Friedman (ISCAS, 1994)

Minimizing Power Dissipation in Non-Zero Skew-Based Clock Distribution Networks. - José Luis Neves; Eby G. Friedman (ISCAS, 1995)

Optimal Clock Skew Scheduling Tolerant to Process Variations. - José Luis Neves; Eby G. Friedman (DAC, 1996)

Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew. - José Luis Neves; Eby G. Friedman (IEEE Trans. Very Large Scale Integr. Syst., 1996)

Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations. - José Luis Neves; Eby G. Friedman (J. VLSI Signal Process., 1997)

Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. - Yehea I. Ismail; Eby G. Friedman; José Luis Neves (Great Lakes Symposium on VLSI, 1998)

Methods for calculating coupling noise in early design: a comparative analysis. - Khalid Rahmat; José Neves 002; Jin-Fuw Lee (ICCD, 1998)

Transient power in CMOS gates driving LC transmission lines. - Yehea I. Ismail; Eby G. Friedman; José Luis Neves (ICECS, 1998)

Power dissipated by CMOS gates driving lossless transmission lines. - Yehea I. Ismail; Eby G. Friedman; José Luis Neves (ISLPED, 1998)

Automated Synthesis of Skew-Based Clock Distribution Networks. - José Luis Neves; Eby G. Friedman (VLSI Design, 1998)

Equivalent Elmore Delay for RLC Trees. - Yehea I. Ismail; Eby G. Friedman; José Luis Neves (DAC, 1999)

Repeater insertion in tree structured inductive interconnect. - Yehea I. Ismail; Eby G. Friedman; José Luis Neves (ICCAD, 1999)

Signal waveform characterization in RLC trees. - Yehea I. Ismail; Eby G. Friedman; José Luis Neves (ISCAS (6), 1999)

Figures of merit to characterize the importance of on-chip inductance. - Yehea I. Ismail; Eby G. Friedman; José Luis Neves (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Buffer Library Selection. - José Luis Neves; Stephen T. Quay (ICCD, 2000)

Equivalent Elmore delay for RLC trees. - Yehea I. Ismail; Eby G. Friedman; José Luis Neves (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Steiner tree optimization for buffers, blockages, and bays. - Charles J. Alpert; Gopal Gandham; Jiang Hu; José Luis Neves; Stephen T. Quay; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Exploiting the on-chip inductance in high-speed clock distribution networks. - Yehea I. Ismail; Eby G. Friedman; José Luis Neves (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Inductance Effects in RLC Trees. - Yehea I. Ismail; Eby G. Friedman; José Luis Neves (J. Circuits Syst. Comput., 2002)

Multi-Session Partitioning for Parallel Timing Optimization. - Jiyoun Kim; José Neves 002; Marios C. Papaefthymiou (PDCAT, 2005)

Parallelizing post-placement timing optimization. - Jiyoun Kim; Marios C. Papaefthymiou; José Luis Neves (IPDPS, 2006)

Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System. - James D. Warnock; Yiu-Hing Chan; Sean M. Carey; Huajun Wen; Patrick J. Meaney; Guenter Gerwig; Howard H. Smith; Yuen H. Chan; John Davis; Paul Bunce; Antonio Pelella; Daniel Rodko; et al. (IEEE J. Solid State Circuits, 2012)

IBM z13 circuit design and methodology. - James D. Warnock; Christopher J. Berry; Michael H. Wood; Leon J. Sigal; Yun-Chan Myung; Guenter Mayer; Mark D. Mayo; Y. Chan; Frank Malgioglio; Gerald Strevig; Charudhattan Nagarajan; Sean M. Carey; et al. (IBM J. Res. Dev., 2015)

IBM z14™: 14nm microprocessor for the next-generation mainframe. - Christopher J. Berry; James D. Warnock; John Isakson; John Badar; Brian Bell 001; Frank Malgioglio; Guenter Mayer; Dina Hamid; Jesse Surprise; David Wolpert 001; Ofer Geva; Bill Huott; et al. (ISSCC, 2018)

IBM z14 design methodology enhancements in the 14-nm technology node. - Christopher J. Berry; James D. Warnock; John Badar; Dean G. Bair; Erwin Behnen; Brian Bell 001; Alper Buyuktosunoglu; Chris Cavitt; Pierce Chuang; Ofer Geva; Dina Hamid; John Isakson; et al. (IBM J. Res. Dev., 2018)