Power-constrained high-frequency circuits for the IBM POWER6 microprocessor. - Brian W. Curran; Eric Fluhr; Jose Paredes; Leon J. Sigal; Joshua Friedrich; Yiu-Hing Chan; Charlie Hwang (IBM J. Res. Dev., 2007)

A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor. - Jürgen Pille; Dieter F. Wendel; Otto Wagner; Rolf Sautter; Wolfgang Penth; Thomas Fröhnel; Stefan Büttner; Otto A. Torreiter; Martin Eckert; Jose Paredes; David Hrusecky; David Ray; et al. (ISSCC, 2010)

POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. - Dieter F. Wendel; Ronald N. Kalla; James D. Warnock; Robert Cargnoni; Sam G. Chu; Joachim G. Clabes; Daniel Dreps; David Hrusecky; Joshua Friedrich; Md. Saiful Islam 004; James A. Kahle; Jens Leenstra; et al. (IEEE J. Solid State Circuits, 2011)

5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. - Eric J. Fluhr; Joshua Friedrich; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; Allen Hall; David Hogenmiller; Frank Malgioglio; Ryan Nett; Jose Paredes; Juergen Pille; et al. (ISSCC, 2014)

IBM POWER8 circuit design and energy optimization. - Victor V. Zyuban; Joshua Friedrich; Daniel M. Dreps; Jürgen Pille; Donald W. Plass; Phillip J. Restle; Zeynep Toprak Deniz; Matthew M. Ziegler; Sam G. Chu; Md. Saiful Islam 004; James D. Warnock; Bob Philhower; et al. (IBM J. Res. Dev., 2015)

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. - Eric J. Fluhr; Steve Baumgartner; David W. Boerstler; John F. Bulzacchelli; Timothy Diemoz; Daniel Dreps; George English; Joshua Friedrich; Anne Gattiker; Tilman Gloekler; Christopher J. Gonzalez; Jason Hibbeler; et al. (IEEE J. Solid State Circuits, 2015)

3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4. - Christopher J. Gonzalez; Eric Fluhr; Daniel Dreps; David Hogenmiller; Rahul M. Rao; Jose Paredes; Michael S. Floyd; Michael A. Sperling; Ryan Kruse; Vinod Ramadurai; Ryan Nett; Md. Saiful Islam 004; et al. (ISSCC, 2017)

The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. - Christopher J. Gonzalez; Michael S. Floyd; Eric Fluhr; Phillip J. Restle; Daniel Dreps; Michael A. Sperling; Rahul M. Rao; David Hogenmiller; Christos Vezyrtzis; Pierce Chuang; Daniel Lewis; Ricardo Escobar; et al. (IEEE J. Solid State Circuits, 2018)

Pulsed Neural Network Plus Parallel Multi-core Approach to Solve Efficiently Big Shortest Path Problems. - Manuel Mejía-Lavalle; Javier Ortiz 001; Alicia Martínez 001; Jose Paredes; Dante Mújica (MICAI, 2019)