A layout defect-sensitivity extractor. - José Pineda de Gyvez; Jochen A. G. Jess (ICCAD, 1989)

On the design and implementation of a wafer yield editor. - José Pineda de Gyvez; Jochen A. G. Jess (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

IC defect sensitivity for footprint-type spot defects. - José Pineda de Gyvez; Chennian Di (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Integrated circuit defect-sensitivity - theory and computational models. - José Pineda de Gyvez (Kluwer, 1993)

Single-Layer CNN Simulator. - Chi-Chien Lee; José Pineda de Gyvez (ISCAS, 1994)

Time-Mulitplexing CNN Simulator. - Chi-Chien Lee; José Pineda de Gyvez (ISCAS, 1994)

Behavioral Testing of Cellular Neural Networks. - John Willis; José Pineda de Gyvez (ISCAS, 1994)

A power supply ramping and current measurement based technique for analog fault diagnosis. - Shyam S. Somayajula; Edgar Sánchez-Sinencio; José Pineda de Gyvez (VTS, 1994)

A Universal Interface Between PC and Neural Networks Hardware. - Apollo Q. Fong; Ajay Kanji; Edgar Sánchez-Sinencio; José Pineda de Gyvez (ISCAS, 1995)

Time Domain Analog Wavelet Transform in Real-Time. - Oscar Moreira-Tamayo; José Pineda de Gyvez (ISCAS, 1995)

Preprocessing operators for image compression using cellular neural networks. - Oscar Moreira-Tamayo; José Pineda de Gyvez (ICNN, 1996)

Time-Multiplexing Scheme for Cellular Neural Networks Based Image Processing. - Apollo Q. Fong; Ajay Kanji; José Pineda de Gyvez (Real Time Imaging, 1996)

Color image processing in a cellular neural-network environment. - Chi-Chien Lee; José Pineda de Gyvez (IEEE Trans. Neural Networks, 1996)

DNA computing based on chaos. - Gabriele Manganaro; José Pineda de Gyvez (ICEC, 1997)

Time multiplexed color image processing based on a CNN with cell-state outputs. - Lei Wang; José Pineda de Gyvez; Edgar Sánchez-Sinencio (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Chaotic generation of PN sequences: a VLSI implementation. - A. Dornbusch; José Pineda de Gyvez (ISCAS (5), 1999)

CMOS cryptosystem using a Lorenz chaotic oscillator. - Octavio A. González; Gunhee Han; José Pineda de Gyvez; Edgar Sánchez-Sinencio (ISCAS (5), 1999)

Subband coding and image compression using CNN. - Oscar Moreira-Tamayo; José Pineda de Gyvez (Int. J. Circuit Theory Appl., 1999)

Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families. - Madhuban Kishor; José Pineda de Gyvez (DFT, 2000)

Real-time wavelet-integrated corrosion detection system for casing pipes. - Jiming Yin; José Pineda de Gyvez; Mi Lu (Integr. Comput. Aided Eng., 2000)

Nonlinear Computability Based on Chaos. - Gabriele Manganaro; José Pineda de Gyvez (Int. J. Bifurc. Chaos, 2000)

Full-signature real-time corrosion detection of underground casing pipes. - Jiming Yin; Mi Lu; José Pineda de Gyvez (IEEE Trans. Instrum. Meas., 2000)

Pre-layout prediction of interconnect manufacturability. - Phillip Christie; José Pineda de Gyvez (SLIP, 2001)

Yield modeling and BEOL fundamentals. - José Pineda de Gyvez (SLIP, 2001)

Average Leakage Current Estimation of CMOS Logic Circuits. - José Pineda de Gyvez; Eric van de Wetering (VTS, 2001)

Resistance Characterization for Weak Open Defects. - Rosa Rodríguez-Montañés; Paul Volf; José Pineda de Gyvez (IEEE Des. Test Comput., 2002)

Process-variability aware delay fault testing of ΔVT and weak-open defects. - Daniel Arumí-Delgado; Rosa Rodríguez-Montañés; José Pineda de Gyvez; Guido Gronthoud (ETW, 2003)

Encoded-Low Swing Technique for Ultra Low Power Interconnect. - Rohini Krishnan; José Pineda de Gyvez; Harry J. M. Veendrick (FPL, 2003)

VDD Ramp Testing for RF Circuits. - José Pineda de Gyvez; Guido Gronthoud; Rashid Amine (ITC, 2003)

An Analog Integrated Circuit Design Laboratory. - Antonio F. Mondragón-Torres; Terry Mayhugh Jr.; José Pineda de Gyvez; José Silva-Martínez; Edgar Sánchez-Sinencio (MSE, 2003)

Threshold Voltage Mismatch (DeltaVT) Fault Modeling. - José Pineda de Gyvez; Rosa Rodríguez-Montañés (VTS, 2003)

Prelayout interconnect yield prediction. - Phillip Christie; José Pineda de Gyvez (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Power Supply Noise Monitor for Signal Integrity Faults. - Josep Rius Vázquez; José Pineda de Gyvez (DATE, 2004)

Low energy FPGA interconnect design. - Rohini Krishnan; José Pineda de Gyvez; Martijn T. Bennebroek (FPGA, 2004)

Technology exploration for adaptive power and frequency scaling in 90nm CMOS. - Maurice Meijer; Francesco Pessolano; José Pineda de Gyvez (ISLPED, 2004)

Power Supply Ramping for Quasi-static Testing of PLLs. - José Pineda de Gyvez; Guido Gronthoud; Cristiano Cenci; Martin Posch; Thomas Burger; Manfred Koller (ITC, 2004)

AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold. - Andrei Pavlov; Manoj Sachdev; José Pineda de Gyvez (ITC, 2004)

Low Energy Switch Block For FPGAs. - Rohini Krishnan; José Pineda de Gyvez (VLSI Design, 2004)

Built-in Current Sensor for ?I{DDQ} Testing of Deep Submicron Digital CMOS ICs. - Josep Rius Vázquez; José Pineda de Gyvez (VTS, 2004)

Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits. - José Pineda de Gyvez; Hans Tuinhout (IEEE J. Solid State Circuits, 2004)

Built-in current sensor for ΔIDDQ testing. - Josep Rius Vázquez; José Pineda de Gyvez (IEEE J. Solid State Circuits, 2004)

Programmable techniques for cell stability test and debug in embedded SRAMs. - Andrei Pavlov; Manoj Sachdev; José Pineda de Gyvez; Mohamed Azimane (CICC, 2005)

Evaluation of signature-based testing of RF/analog circuits. - Amir Zjajo; José Pineda de Gyvez (ETS, 2005)

Limits to performance spread tuning using adaptive voltage and body biasing. - Maurice Meijer; Francesco Pessolano; José Pineda de Gyvez (ISCAS (1), 2005)

Glitch-free discretely programmable clock generation on chip. - Maurice Meijer; Francesco Pessolano; José Pineda de Gyvez (ISCAS (2), 2005)

On-chip digital power supply control for system-on-chip applications. - Maurice Meijer; José Pineda de Gyvez; Ralph Otten (ISLPED, 2005)

Word line pulsing technique for stability fault detection in SRAM cells. - Andrei Pavlov; Mohamed Azimane; José Pineda de Gyvez; Manoj Sachdev (ITC, 2005)

Functional vs. multi-VDD testing of RF circuits. - Estella Silva; José Pineda de Gyvez; Guido Gronthoud (ITC, 2005)

Power-scan chain: design for analog testability. - Amir Zjajo; Henk Jan Bergveld; Rodger Schuttert; José Pineda de Gyvez (ITC, 2005)

Multi-VDD Testing for Analog Circuits. - José Pineda de Gyvez; Guido Gronthoud; Rashid Amine (J. Electron. Test., 2005)

A capacitor cross-coupled common-gate low-noise amplifier. - Wei Zhuo 003; Xiaoyong Li 001; Sudip Shekhar; Sherif H. K. Embabi; José Pineda de Gyvez; David J. Allstot; Edgar Sánchez-Sinencio (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

Testing and Diagnosis of Power Switches in SOCs. - Sandeep Kumar Goel; Maurice Meijer; José Pineda de Gyvez (ETS, 2006)

Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits. - Amir Zjajo; José Pineda de Gyvez; Guido Gronthoud (J. Electron. Test., 2006)

An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. - Josep Rius 001; Maurice Meijer; José Pineda de Gyvez (J. Low Power Electron., 2006)

Weak Cell Detection in Deep-Submicron SRAMs: A Programmable Detection Technique. - Andrei Pavlov; Manoj Sachdev; José Pineda de Gyvez (IEEE J. Solid State Circuits, 2006)

Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits. - Amir Zjajo; Manuel J. Barragan Asian; José Pineda de Gyvez (DATE, 2007)

Vt balancing and device sizing towards high yield of sub-threshold static logic gates. - Yu Pu; José de Jesus Pineda de Gyvez; Henk Corporaal; Yajun Ha (ISLPED, 2007)

Efficient testing and diagnosis of faulty power switches in SOCs. - Sandeep Kumar Goel; Maurice Meijer; José Pineda de Gyvez (IET Comput. Digit. Tech., 2007)

Statistical noise margin estimation for sub-threshold combinational circuits. - Yu Pu; José de Jesus Pineda de Gyvez; Henk Corporaal; Yajun Ha (ASP-DAC, 2008)

Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters. - Amir Zjajo; José Pineda de Gyvez (DATE, 2008)

Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm. - Amir Zjajo; Shaji Krishnan; José Pineda de Gyvez (DDECS, 2008)

Calibration and Debugging of Multi-step Analog to Digital Converters. - Amir Zjajo; José Pineda de Gyvez (DELTA, 2008)

An energy-aware multiplier based on a Configurable-Reuse of points design methodology. - Sebastian M. Londono; José Pineda de Gyvez (ICECS, 2009)

Dynamic voltage scaling based on supply current tracking using fuzzy Logic controller. - Hamid Reza Pourshaghaghi; José Pineda de Gyvez (ICECS, 2009)

An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply. - Yu Pu; José de Jesus Pineda de Gyvez; Henk Corporaal; Yajun Ha (ISSCC, 2009)

Analog Automatic Test Pattern Generation for Quasi-Static Structural Test. - Amir Zjajo; José Pineda de Gyvez (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Power-performance optimization using fuzzy control of simultaneous supply voltage and body biasing scaling. - Hamid Reza Pourshaghaghi; José Pineda de Gyvez (ICECS, 2010)

A forward body bias generator for digital CMOS circuits with supply voltage scaling. - Maurice Meijer; José Pineda de Gyvez; Ben Kup; Bert van Uden; Peter Bastiaansen; Marco Lammers; Maarten Vertregt (ISCAS, 2010)

Body bias driven design synthesis for optimum performance per area. - Maurice Meijer; José Pineda de Gyvez (ISQED, 2010)

Ultra-Low-Power Digital Design with Body Biasing for Low Area and Performance-Efficient Operation. - Maurice Meijer; José Pineda de Gyvez; Ajay Kapoor (J. Low Power Electron., 2010)

An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage. - Yu Pu; José de Jesus Pineda de Gyvez; Henk Corporaal; Yajun Ha (IEEE J. Solid State Circuits, 2010)

Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage. - Bo Liu; Hamid Reza Pourshaghaghi; Sebastian M. Londono; José Pineda de Gyvez (DSD, 2011)

A 1.2v 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOs. - Amir Zjajo; José Pineda de Gyvez (ISLPED, 2011)

Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs. - Amir Zjajo; Qin Tang; Michel Berkelaar; José Pineda de Gyvez; Alessandro Di Bucchianico; Nick van der Meijs (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Standard cell sizing for subthreshold operation. - Bo Liu; Maryam Ashouei; Jos Huisken; José Pineda de Gyvez (DAC, 2012)

Sliding-Mode Control to Compensate PVT Variations in dual core systems. - Hamid Reza Pourshaghaghi; Hamed Fatemi; José Pineda de Gyvez (DATE, 2012)

A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation. - Sebastian M. Londono; José Pineda de Gyvez (SoCC, 2012)

Digital Adaptive Calibration of Multi-Step Analog to Digital Converters. - Amir Zjajo; Manuel J. Barragan Asian; José Pineda de Gyvez (J. Low Power Electron., 2012)

Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS. - Amir Zjajo; Manuel J. Barragan Asian; José Pineda de Gyvez (IEEE Trans. Instrum. Meas., 2012)

Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits. - Maurice Meijer; José Pineda de Gyvez (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using Carry-Save format numbers. - Yanxiang Huang; Ajay Kapoor; Robert Rutten; José Pineda de Gyvez (NORCHIP, 2013)

Fuzzy-Controlled Voltage Scaling Based on Supply Current Tracking. - Hamid Reza Pourshaghaghi; José Pineda de Gyvez (IEEE Trans. Computers, 2013)

Architectural Analysis for Wirelessly Powered Computing Platforms. - Ajay Kapoor; José Pineda de Gyvez (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Standard cell library tuning for variability tolerant designs. - Sebastien Fabrie; Juan Diego Echeverri; Maarten Vertregt; José Pineda de Gyvez (DATE, 2014)

Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling. - Yu Pu; Juan Diego Echeverri; Maurice Meijer; José Pineda de Gyvez (DATE, 2014)

Sub-threshold custom standard cell library validation. - Bo Liu; Maryam Ashouei; Tobias Gemmeke; José Pineda de Gyvez (ISQED, 2014)

Digital Systems Power Management for High Performance Mixed Signal Platforms. - Ajay Kapoor; Cas Groot; Gerard Villar Pique; Hamed Fatemi; Juan Diego Echeverri; Leo Sevat; Maarten Vertregt; Maurice Meijer; Vibhu Sharma; Yu Pu; José Pineda de Gyvez (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Reducing energy consumption in microcontroller-based platforms with low design margin co-processors. - Andres Gomez 001; Christian Pinto; Andrea Bartolini; Davide Rossi; Luca Benini; Hamed Fatemi; José Pineda de Gyvez (DATE, 2015)

Supervised learning based model for predicting variability-induced timing errors. - Xun Jiao; Abbas Rahimi; Balakrishnan Narayanaswamy; Hamed Fatemi; José Pineda de Gyvez; Rajesh K. Gupta 001 (NEWCAS, 2015)

Slack-aware timing margin redistribution technique utilizing error avoidance flip-flops and time borrowing. - Mini Jayakrishnan; Alan Chang; José Pineda de Gyvez; Tae-Hyoung Kim (VLSI-SoC, 2015)

A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain with Carry-Save format numbers. - Yanxiang Huang; Ajay Kapoor; Robert Rutten; José Pineda de Gyvez (Microprocess. Microsystems, 2015)

An Improved Methodology for Resilient Design Implementation. - Andrew B. Kahng; Seokhyeong Kang; Jiajia Li 002; José Pineda de Gyvez (ACM Trans. Design Autom. Electr. Syst., 2015)

Lower power by voltage stacking: a fine-grained system design approach. - Kristof Blutman; Ajay Kapoor; Jacinto Garcia Martinez; Hamed Fatemi; José Pineda de Gyvez (DAC, 2016)

Circuit valorization in the IC design ecosystem. - José Pineda de Gyvez; Hamed Fatemi; Maarten Vertregt (ICCAD, 2016)

A microcontroller with 96% power-conversion efficiency using stacked voltage domains. - Kristof Blutman; Ajay Kapoor; Arjun Majumdar; Jacinto Garcia Martinez; Juan Diego Echeverri; Leo Sevat; Arnoud P. van der Wel; Hamed Fatemi; José Pineda de Gyvez; Kofi A. A. Makinwa (VLSI Circuits, 2016)

Floorplan and placement methodology for improved energy reduction in stacked power-domain design. - Kristof Blutman; Hamed Fatemi; Andrew B. Kahng; Ajay Kapoor; Jiajia Li 002; José Pineda de Gyvez (ASP-DAC, 2017)

A scan-chain based state retention methodology for IoT processors operating on intermittent energy. - Pascal Alexander Hager; Hamed Fatemi; José Pineda de Gyvez; Luca Benini (DATE, 2017)

An analytical model for interdependent setup/hold-time characterization of flip-flops. - Hadi Ahmadi Balef; Hailong Jiao; José Pineda de Gyvez; Kees Goossens (ISQED, 2017)

Reconfigurable Support Vector Machine Classifier with Approximate Computing. - Martin Van Leussen; Jos Huisken; Lei Wang; Hailong Jiao; José Pineda de Gyvez (ISVLSI, 2017)

A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling. - Kristof Blutman; Ajay Kapoor; Arjun Majumdar; Jacinto Garcia Martinez; Juan Diego Echeverri; Leo Sevat; Arnoud P. van der Wel; Hamed Fatemi; Kofi A. A. Makinwa; José Pineda de Gyvez (IEEE J. Solid State Circuits, 2017)

Increasing the energy efficiency of microcontroller platforms with low-design margin co-processors. - Andres Gomez 001; Andrea Bartolini; Davide Rossi; Baris Can Kara; Hamed Fatemi; José Pineda de Gyvez; Luca Benini (Microprocess. Microsystems, 2017)

Logic Design Partitioning for Stacked Power Domains. - Kristof Blutman; Hamed Fatemi; Ajay Kapoor; Andrew B. Kahng; Jiajia Li 002; José Pineda de Gyvez (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Effective In-Situ Chip Health Monitoring with Selective Monitor Insertion Along Timing Paths. - Hadi Ahmadi Balef; Hamed Fatemi; Kees Goossens; José Pineda de Gyvez (ACM Great Lakes Symposium on VLSI, 2018)

Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design. - Kamlesh Singh; Omar Alejandro Rodriguez Rosas; Hailong Jiao; Jos Huisken; José Pineda de Gyvez (ISCAS, 2018)

Low power latch based design with smart retiming. - Kamlesh Singh; Hailong Jiao; Jos Huisken; Hamed Fatemi; José Pineda de Gyvez (ISQED, 2018)

Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCs. - P. Anagnostou; Andres Gomez 001; Pascal A. Hager; Hamed Fatemi; José Pineda de Gyvez; Lothar Thiele; Luca Benini (PATMOS, 2018)

CLIM: A Cross-Level Workload-Aware Timing Error Prediction Model for Functional Units. - Xun Jiao; Abbas Rahimi; Yu Jiang 001; Jianguo Wang 001; Hamed Fatemi; José Pineda de Gyvez; Rajesh K. Gupta 001 (IEEE Trans. Computers, 2018)

Chip Health Tracking Using Dynamic In-Situ Delay Monitoring. - Hadi Ahmadi Balef; Kees Goossens; José Pineda de Gyvez (DATE, 2019)

Trading Digital Accuracy for Power in an RSSI Computation of a Sensor Network Transceiver. - Paul Detterer; Cumhur Erdin; Majid Nabi; José Pineda de Gyvez; Twan Basten; Hailong Jiao (DATE, 2019)

Keyword Spotting using Time-Domain Features in a Temporal Convolutional Network. - Emad A. Ibrahim; Jos Huisken; Hamed Fatemi; José Pineda de Gyvez (DSD, 2019)

PRESS/HOLD/RELEASE Ultrasonic Gestures and Low Complexity Recognition Based on TCN. - Emad A. Ibrahim; Min Li; José Pineda de Gyvez (SiPS, 2019)

Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation. - Kamlesh Singh; Barry de Bruin; Jos Huisken; Hailong Jiao; José Pineda de Gyvez (SoCC, 2019)

Energy and power awareness in hardware schedulers for energy harvesting IoT SoCs. - P. Anagnostou; Andres Gomez 001; Pascal A. Hager; Hamed Fatemi; José Pineda de Gyvez; Lothar Thiele; Luca Benini (Integr., 2019)

Enhancing sensitivity-based power reduction for an industry IC design context. - Hamed Fatemi; Andrew B. Kahng; Hyein Lee 001; Jiajia Li 002; José Pineda de Gyvez (Integr., 2019)

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. - Massimo Alioto; Magdy S. Abadir; Tughrul Arslan; Chirn Chye Boon; Andreas Burg 001; Chip-Hong Chang; Meng-Fan Chang; Yao-Wen Chang; Poki Chen; Pasquale Corsonello; Paolo Crovetti; Shiro Dosho; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention. - Hadi Ahmadi Balef; Hamed Fatemi; Kees Goossens; José Pineda de Gyvez (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Trading Sensitivity for Power in an IEEE 802.15.4 Conformant Adequate Demodulator. - Paul Detterer; Cumhur Erdin; Jos Huisken; Hailong Jiao; Majid Nabi; Twan Basten; José Pineda de Gyvez (DATE, 2020)

Low Complexity Multi-directional In-Air Ultrasonic Gesture Recognition Using a TCN. - Emad A. Ibrahim; Marc Geilen; Jos Huisken; Min Li; José Pineda de Gyvez (DATE, 2020)

An Electromagnetic Energy Harvester and Power Management in 28-nm FDSOI for IoT. - Shima Sedighiani; Kamlesh Singh; Jos Huisken; Roel Jordans; Pieter Harpe; José Pineda de Gyvez (MECO, 2020)

Optimal bounded-skew steiner trees to minimize maximum k-active dynamic power. - Hamed Fatemi; Andrew B. Kahng; Minsoo Kim; José Pineda de Gyvez (SLIP, 2020)

Multi-Angle Fusion for Low-Cost Near-Field Ultrasonic in-Air Gesture Recognition. - Emad A. Ibrahim; Marc Geilen; Min Li; José Pineda de Gyvez (IEEE Access, 2020)

Heuristic Methods for Fine-Grain Exploitation of FDSOI. - Hamed Fatemi; Andrew B. Kahng; Hyein Lee 001; José Pineda de Gyvez (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A Low Power Fully-Digital Multi-Level Voltage Monitor Operating in a Wide Voltage Range for Energy Harvesting IoT. - Shima Sedighiani; Kamlesh Singh; Roel Jordans; Pieter Harpe; José Pineda de Gyvez (ISQED, 2021)

Multi-Level Optimization of an Ultra-Low Power BrainWave System for Non-Convulsive Seizure Detection. - Barry de Bruin; Kamlesh Singh; Ying Wang 072; Jos Huisken; José Pineda de Gyvez; Henk Corporaal (IEEE Trans. Biomed. Circuits Syst., 2021)

Twenty Years of Near/Sub-Threshold Design Trends and Enablement. - Kamlesh Singh; José Pineda de Gyvez (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Converter-Free Power Delivery Using Voltage Stacking for Near/Subthreshold Operation. - Kamlesh Singh; Barry de Bruin; Hailong Jiao; Jos Huisken; Henk Corporaal; José Pineda de Gyvez (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods. - Shima Sedighiani; Kamlesh Singh; Roel Jordans; Pieter Harpe; José Pineda de Gyvez (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An Ultra-Low-Leakage Microcontroller With Configurable Power Management for Energy Harvesting IoT Devices. - Shima Sedighiani; Bram van Bolderik; Barry de Bruin; Kamlesh Singh; Roel Jordans; Pieter Harpe; José Pineda de Gyvez (IEEE Access, 2025)