A Reorder Buffer Design for High Performance Processors. - Jose Raul Garcia Ordaz; Marco Antonio Ramírez Salinas; Luis A. Villa Vargas; Herón Molina Lozano; Cuauhtémoc Peredo Macías (Computación y Sistemas, 2012)

soft-NEON: A study on replacing the NEON engine of an ARM SoC with a reconfigurable fabric. - Jose Raul Garcia Ordaz; Dirk Koch (ASAP, 2016)

Making a case for an ARM Cortex-A9 CPU interlay replacing the NEON SIMD unit. - Jose Raul Garcia Ordaz; Dirk Koch (FPL, 2017)

A security library for FPGA interlays. - Anuj Vaishnav; Jose Raul Garcia Ordaz; Dirk Koch (FPL, 2017)

HLS Compilation for CPU Interlays. - Jose Raul Garcia Ordaz; Dirk Koch (HEART, 2017)

A Soft Dual-Processor System with a Partially Run-Time Reconfigurable Shared 128-Bit SIMD Engine. - Jose Raul Garcia Ordaz; Dirk Koch (ASAP, 2018)

Dynamic CPU ISA customizations through FPGA interlays. - Jose Raul Garcia Ordaz (2018)