Programmable switched-capacitor bump equalizer architecture. - J. Francisco Duque-Carrillo; Jose Silva-Martinez; Edgar Sánchez-Sinencio (IEEE J. Solid State Circuits, 1990)

A large-signal very low-distortion transconductor for high-frequency continuous-time filters. - Jose Silva-Martinez; Michel S. J. Steyaert; Willy M. C. Sansen (IEEE J. Solid State Circuits, 1991)

Design techniques for high-performance full-CMOS OTA-RC continuous-time filters. - Jose Silva-Martinez; Michel S. J. Steyaert; Willy Sansen (IEEE J. Solid State Circuits, 1992)

A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chip automatic tuning. - Jose Silva-Martinez; Michel S. J. Steyaert; Willy Sansen (IEEE J. Solid State Circuits, 1992)

High-performance CMOS continuous-time filters. - José Silva-Martínez; Michiel Steyaert; Willy M. C. Sansen (Kluwer, 1993)

Effect of the Transistor Mismatches on the Performance of Fully-Differential OTAS. - José Silva-Martínez (ISCAS, 1994)

A Programmable Switched-Capacitor Filter. - José Silva-Martínez (ISCAS, 1994)

A CMOS Preamplifier for Electret Microphones. - José Silva-Martínez; Jorge Salcedo-Suñer (ISCAS, 1995)

Efficient clock recovery architecture. - Marcia G. Méndez-Rivera; Ari Yakov Valero-López; José Silva-Martínez; Edgar Sánchez-Sinencio (ICECS, 1998)

A 4 Hz low-pass continuous-time filter. - Sergio A. Solis-Bustos; José Silva-Martínez (ICECS, 1998)

Transimpedance amplifiers for optical fiber systems based on common-base transistors. - J. Martínez-Castillo; José Silva-Martínez (ISCAS (6), 1999)

Design considerations for high performance very low frequency filters. - José Silva-Martínez; S. Solis-Bustos (ISCAS (2), 1999)

A fully-programmable temperature-compensated analogue circuit for Gaussian functions. - Miguel Melendez-Rodriguez; José Silva-Martínez (ISCAS, 2000)

Different operational transconductance amplifier topologies for obtaining very small transconductances. - Anand Veeravalli; Edgar Sánchez-Sinencio; José Silva-Martínez (ISCAS, 2000)

A feedforward compensation scheme for high gain wideband amplifiers. - Bharath Kumar Thandri; José Silva-Martínez; Franco Maloberti (ICECS, 2001)

Linear cellular neural networks. - Federico Lobato-Lopez; José Silva-Martínez; Edgar Sánchez-Sinencio (ISCAS (3), 2001)

A 150 MHz continuous-time seventh order 0.05° equiripple linear phase filter with automatic tuning system. - Adan Lopez-Martinez; Regina Antonio-Chavez; José Silva-Martínez (ISCAS (1), 2001)

A low voltage operational transconductance amplifier using common mode feedforward for high frequency switched capacitor circuits. - Asit Shankar; José Silva-Martínez; Edgar Sánchez-Sinencio (ISCAS (1), 2001)

A 2.1GHz 1.3V 5mW programmable Q-enhancement LC bandpass biquad in 0.35μm CMOS. - Fikret Duelgel; Edgar Sánchez-Sinencio; Jose Silva-Martinez (CICC, 2002)

A high-Q, switched-capacitor filter with reduced capacitance spread using a randomized nonuniform sampling technique. - Jozef Adut; José Silva-Martínez (ISCAS (4), 2002)

A robust frequency compensation scheme for LDO regulators. - Chaitanya K. Chava; José Silva-Martínez (ISCAS (5), 2002)

A 1.8V CMOS, 80-200MHz continuous-time 4th order 0.05° equiripple linear phase filter with automatic tuning system. - Mingdeng Chen; José Silva-Martínez; Shahriar Rokhsaz; Moises E. Robinson (ISCAS (5), 2002)

On-chip spectrum analyzer for built-in testing analog ICs. - Marcia G. Méndez-Rivera; José Silva-Martínez; Edgar Sánchez-Sinencio (ISCAS (5), 2002)

A 2.1-GHz monolithic frequency synthesizer with robust phase switching prescaler and loop capacitance scaling. - Keliu Shu; Edgar Sánchez-Sinencio; José Silva-Martínez (ISCAS (4), 2002)

Transconductance amplifier structures with very small transconductances: a comparative design approach. - Anand Veeravalli; Edgar Sánchez-Sinencio; José Silva-Martínez (IEEE J. Solid State Circuits, 2002)

A CMOS transconductance amplifier architecture with wide tuning range for very low frequency applications. - Anand Veeravalli; Edgar Sánchez-Sinencio; José Silva-Martínez (IEEE J. Solid State Circuits, 2002)

OTA linearity enhancement technique for high frequency applications with IM3 below -65dB. - Artur J. Lewinski; José Silva-Martínez (CICC, 2003)

A 58dB SNR 6th order broadband 10.7 MHz SC ladder filter. - José Silva-Martínez; Joseph Adut; Miguel Rocha-Pérez (CICC, 2003)

A 92MHz, 80dB peak SNR SC bandpass ΣΔ modulator based on a high GBW OTA with no Miller capacitors in 0.35μm CMOS technology. - Bharath Kumar Thandri; José Silva-Martínez; José Miguel Rocha-Pérez; Jing Wang (CICC, 2003)

Cascode transconductance amplifiers for HF switched-capacitor applications. - Jozef Adut; José Silva-Martínez (ISCAS (1), 2003)

An Analog Integrated Circuit Design Laboratory. - Antonio F. Mondragón-Torres; Terry Mayhugh Jr.; José Pineda de Gyvez; José Silva-Martínez; Edgar Sánchez-Sinencio (MSE, 2003)

Compact sub-hertz OTA-C filter design with interface-trap charge pump. - Adriana Becker-Gomez; Ugur Çilingiroglu; José Silva-Martínez (IEEE J. Solid State Circuits, 2003)

A 2-Vpp 80-200-MHz fourth-order continuous-time linear phase filter with automatic frequency tuning. - Mingdeng Chen; José Silva-Martínez; Shahriar Rokhsaz; Moises E. Robinson (IEEE J. Solid State Circuits, 2003)

A 1.3-V 5-mW fully integrated tunable bandpass filter at 2.1 GHz in 0.35-μm CMOS. - Fikret Dulger; Edgar Sánchez-Sinencio; José Silva-Martínez (IEEE J. Solid State Circuits, 2003)

A fully balanced pseudo-differential OTA with common-mode feedforward and inherent common-mode feedback detector. - Ahmed Nader Mohieldin; Edgar Sánchez-Sinencio; José Silva-Martínez (IEEE J. Solid State Circuits, 2003)

A 2.7-V 1.8-GHz fourth-order tunable LC bandpass filter based on emulation of magnetically coupled resonators. - Ahmed N. Mohieldin; Edgar Sánchez-Sinencio; José Silva-Martínez (IEEE J. Solid State Circuits, 2003)

A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier. - Keliu Shu; Edgar Sánchez-Sinencio; José Silva-Martínez; Sherif H. K. Embabi (IEEE J. Solid State Circuits, 2003)

A 60-mW 200-MHz continuous-time seventh-order linear phase filter with on-chip automatic tuning system. - José Silva-Martínez; Joseph Adut; José Miguel Rocha-Pérez; Moises E. Robinson; Shahriar Rokhsaz (IEEE J. Solid State Circuits, 2003)

A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors. - Bharath Kumar Thandri; José Silva-Martínez (IEEE J. Solid State Circuits, 2003)

Nonlinear effects in pseudo differential OTAs with CMFB. - A. N. Mohieldin; Edgar Sánchez-Sinencio; José Silva-Martínez (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

A 500 MHz OTA-C 4th order lowpass filter with class AB CMFB in 0.35 μm CMOS technology. - Pankaj Pandey; José Silva-Martínez; Xuemei Liu (CICC, 2004)

6.8 mW 2.5 Gb/s and 42.5 mW 5 Gb/s 1: 8 CMOS demultiplexers. - Shanfeng Cheng; José Silva-Martínez (ISCAS (4), 2004)

Bandwidth enhancement of multi-stage amplifiers using active feedback. - M. Reza Samadi; Aydin I. Karsilayan; José Silva-Martínez (ISCAS (1), 2004)

An On-Chip Transfer Function Characterization System for Analog Built-in Testing. - Alberto Valdes-Garcia; José Silva-Martínez; Edgar Sánchez-Sinencio (VTS, 2004)

A frequency compensation scheme for LDO voltage regulators. - Chaitanya K. Chava; José Silva-Martínez (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

OTA linearity enhancement technique for high frequency applications with IM3 below -65 dB. - Artur J. Lewinski; José Silva-Martínez (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers. - Alberto Valdes-Garcia; Radhika Venkatasubramanian; Rangakrishnan Srinivasan; José Silva-Martínez; Edgar Sánchez-Sinencio (VTS, 2005)

An On-Chip Spectrum Analyzer for Analog Built-In Testing. - Marcia G. Méndez-Rivera; Alberto Valdes-Garcia; José Silva-Martínez; Edgar Sánchez-Sinencio (J. Electron. Test., 2005)

Low-voltage low-power LVDS drivers. - Mingdeng Chen; Jose Silva-Martinez; Michael Nix; Moises E. Robinson (IEEE J. Solid State Circuits, 2005)

Continuous-time common-mode feedback for high-speed switched-capacitor networks. - David Hernandez-Garduno; Jose Silva-Martinez (IEEE J. Solid State Circuits, 2005)

On-Chip Testing Techniques for RF Wireless Transceivers. - Alberto Valdes-Garcia; José Silva-Martínez; Edgar Sánchez-Sinencio (IEEE Des. Test Comput., 2006)

An Integrated Frequency Response Characterization System With a Digital Interface for Analog Testing. - Alberto Valdes-Garcia; Faisal Abdel-Latif Hussien; José Silva-Martínez; Edgar Sánchez-Sinencio (IEEE J. Solid State Circuits, 2006)

An overview of feed-forward design techniques for high-gain wideband operational transconductance amplifiers. - Bharath Kumar Thandri; José Silva-Martínez (Microelectron. J., 2006)

A 10.7-MHz sixth-order SC ladder filter in 0.35-μm CMOS technology. - Jozef Adut; José Silva-Martínez; Miguel Rocha-Pérez (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Quasi Rail-to-Rail Very Low-Voltage OPAMP With a Single pMOS Input Differential Pair. - David Báez-Villegas; José Silva-Martínez (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Frequency-dependent harmonic-distortion analysis of a linearized cross-coupled CMOS OTA and its application to OTA-C filters. - Jianlong Chen; Edgar Sánchez-Sinencio; José Silva-Martínez (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Design and Analysis of an Ultrahigh-Speed Glitch-Free Fully Differential Charge Pump With Minimum Output Current Variation and Accurate Matching. - Shanfeng Cheng; Haitao Tong; José Silva-Martínez; Aydin I. Karsilayan (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A High-Frequency Transconductor Using a Robust Nonlinearity Cancellation. - Artur J. Lewinski; José Silva-Martínez (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A CMOS 140-mW fourth-order continuous-time low-pass filter stabilized with a class AB common-mode feedback operating at 550 MHz. - Pankaj Pandey; José Silva-Martínez; Xuemei Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

A 92-MHz 13-bit IF digitizer using optimized SC integrators in 0.35-μm CMOS technology. - Bharath Kumar Thandri; José Silva-Martínez (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A CMOS 1Gb/s 5-Tap Transversal Equalizer Based on Inductorless 3rd-Order Delay Cells. - David Hernandez-Garduno; José Silva-Martínez (ISSCC, 2007)

A Fully Differential Low-Power Divide-by-8 Injection-Locked Frequency Divider Up to 18 GHz. - Shanfeng Cheng; Haitao Tong; José Silva-Martínez; Aydin Ilker Karsilayan (IEEE J. Solid State Circuits, 2007)

A 1.1 GHz Fifth Order Active-LC Butterworth Type Equalizing Filter. - Vijay Dhanasekaran; Manisha Gambhir; José Silva-Martínez; Edgar Sánchez-Sinencio (IEEE J. Solid State Circuits, 2007)

A 63 dB SNR, 75-mW Bandpass RF ΣΔ ADC at 950 MHz Using 3.8-GHz Clock in 0.25-µm SiGe BiCMOS Technology. - Bharath Kumar Thandri; José Silva-Martínez (IEEE J. Solid State Circuits, 2007)

An 11-Band 3-10 GHz Receiver in SiGe BiCMOS for Multiband OFDM UWB Communication. - Alberto Valdes-Garcia; Chinmaya Mishra; Faramarz Bahmani; José Silva-Martínez; Edgar Sánchez-Sinencio (IEEE J. Solid State Circuits, 2007)

A High Dynamic Range CMOS Variable Gain Amplifier for Mobile DTV Tuner. - Jianhong Xiao; Iuri Mehr; José Silva-Martínez (IEEE J. Solid State Circuits, 2007)

Steady-State Analysis of Phase-Locked Loops Using Binary Phase Detector. - Shanfeng Cheng; Haitao Tong; José Silva-Martínez; Aydin I. Karsilayan (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Low-Power Architecture and Circuit Techniques for High-Boost Wide-Band Gm-C Filters. - Manisha Gambhir; Vijay Dhanasekaran; José Silva-Martínez; Edgar Sánchez-Sinencio (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Estimation of Aliasing Effects Due to Periodical Nonuniform Individual Sampling in High-Q Switched-Capacitor Filters. - David Hernandez-Garduno; José Silva-Martínez; José L. Ausín (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A 30-MHz Fifth-Order Elliptic Low-Pass CMOS Filter With 65-dB Spurious-Free Dynamic Range. - Artur J. Lewinski; José Silva-Martínez (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Full On-Chip CMOS Low-Dropout Voltage Regulator. - Robert Jon Milliken; José Silva-Martínez; Edgar Sánchez-Sinencio (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

An Injection-Locked Frequency Divider With Multiple Highly Nonlinear Injection Stages and Large Division Ratios. - Haitao Tong; Shanfeng Cheng; Aydin I. Karsilayan; José Silva-Martínez (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting. - Jianhong Xiao; Guang Zhang; Tianwei Li; José Silva-Martínez (VLSI Design, 2007)

A low power 1.3GHz dual-path current mode Gm-C filter. - Manisha Gambhir; Vijay Dhanasekaran; José Silva-Martínez; Edgar Sánchez-Sinencio (CICC, 2008)

A 1.2mW 1.6Vpp-Swing Class-AB 16Ω Headphone Driver Capable of Handling Load Capacitance up to 22nF. - Vijay Dhanasekaran; José Silva-Martínez; Edgar Sánchez-Sinencio (ISSCC, 2008)

A CMOS 1 Gb/s 5-Tap Fractionally-Spaced Equalizer. - David Hernandez-Garduno; José Silva-Martínez (IEEE J. Solid State Circuits, 2008)

A Current Injection Built-In Test Technique for RF Low-Noise Amplifiers. - Xiaohua Fan; Marvin Onabajo; Félix O. Fernandez-Rodriguez; José Silva-Martínez; Edgar Sánchez-Sinencio (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A Full On-Chip CMOS Clock-and-Data Recovery IC for OC-192 Applications. - Jinghua Li; José Silva-Martínez; Brian Brunn; Shahriar Rokhsaz; Moises E. Robinson (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Applications of Multipath Transform-Domain Charge-Sampling Wide-Band Receivers. - Pradeep Kotte Prakasam; Mandar Kulkarni; Xi Chen; Zhuizhuan Yu; Sebastian Hoyos; José Silva-Martínez; Edgar Sánchez-Sinencio (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A Broadband CMOS Amplitude Detector for On-Chip RF Measurements. - Alberto Valdes-Garcia; Radhika Venkatasubramanian; José Silva-Martínez; Edgar Sánchez-Sinencio (IEEE Trans. Instrum. Meas., 2008)

A 1.8V, sub-mW, over 100% locking range, divide-by-3 and 7 complementary-injection-locked 4 GHz frequency divider. - Yung-Chung Lo; Hsien-Pu Chen; José Silva-Martínez; Sebastian Hoyos (CICC, 2009)

A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element. - Vijay Dhanasekaran; Manisha Gambhir; Mohamed M. Elsayed; Edgar Sánchez-Sinencio; José Silva-Martínez; Chinmaya Mishra; Lei Chen; Erik Pankratz (ISSCC, 2009)

Non-invasive RF built-in testing using on-chip temperature sensors. - Eduardo Aldrete-Vidrio; Marvin Onabajo; Josep Altet; Diego Mateo; José Silva-Martínez (ITC, 2009)

The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier. - Rida S. Assaad; José Silva-Martínez (IEEE J. Solid State Circuits, 2009)

Design of Three-Stage Class-AB 16ΩHeadphone Driver Capable of Handling Wide Range of Load Capacitance. - Vijay Dhanasekaran; José Silva-Martínez; Edgar Sánchez-Sinencio (IEEE J. Solid State Circuits, 2009)

System and Circuit Design for an MB-OFDM UWB Frequency Synthesizer. - Chinmaya Mishra; Alberto Valdes-Garcia; Edgar Sánchez-Sinencio; José Silva-Martínez (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

An On-Chip Loopback Block for RF Transceiver Built-In Test. - Marvin Onabajo; José Silva-Martínez; Félix O. Fernandez-Rodriguez; Edgar Sánchez-Sinencio (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A Graphical Approach to Teaching Amplifier Design at the Undergraduate Level. - Rida S. Assaad; José Silva-Martínez (IEEE Trans. Educ., 2009)

Recent Advances on the Design of High-Gain Wideband Operational Transconductance Amplifiers. - Rida S. Assaad; José Silva-Martínez (VLSI Design, 2009)

A broadband 470-862 MHz direct conversion CMOS receiver. - Raghavendra Kulkarni; Jusung Kim; Hyung-Joon Jeon; José Silva-Martínez; Jianhong Xiao (ISCAS, 2010)

A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback. - Cho-Ying Lu; Marvin Onabajo; Venkata Gadde; Yung-Chung Lo; Hsien-Pu Chen; Vijayaramalingam Periasamy; José Silva-Martínez (IEEE J. Solid State Circuits, 2010)

A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth. - Cho-Ying Lu; Jose Fabian Silva-Rivas; Praveena Kode; José Silva-Martínez; Sebastian Hoyos (IEEE J. Solid State Circuits, 2010)

Attenuation-Predistortion Linearization of CMOS OTAs With Digital Correction of Process Variations in OTA-C Filter Applications. - Mohamed Mobarak; Marvin Onabajo; José Silva-Martínez; Edgar Sánchez-Sinencio (IEEE J. Solid State Circuits, 2010)

Fully balanced low-noise transconductance amplifiers with P1dB > 0dBm in 45nm CMOS. - Hemasundar Mohan Geddada; José Silva-Martínez; Stewart S. Taylor (ESSCIRC, 2011)

Voltage mode driver for low power transmission of high speed serial AER Links. - Carlos Zamarreño-Ramos; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco; Raghavendra Kulkarni; José Silva-Martínez (ISCAS, 2011)

Survey of Robustness Enhancement Techniques for Wireless Systems-on-a-Chip and Study of Temperature as Observable for Process Variations. - Marvin Onabajo; Didac Gómez; Eduardo Aldrete-Vidrio; Josep Altet; Diego Mateo; José Silva-Martínez (J. Electron. Test., 2011)

A Continuous Time Multi-Bit Delta Sigma ADC Using Time Domain Quantizer and Feedback Element. - Vijay Dhanasekaran; Manisha Gambhir; Mohamed M. Elsayed; Edgar Sánchez-Sinencio; José Silva-Martínez; Chinmaya Mishra; Lei Chen; Erik Pankratz (IEEE J. Solid State Circuits, 2011)

A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based Sigma Delta Modulator. - Mohamed M. Elsayed; Vijay Dhanasekaran; Manisha Gambhir; José Silva-Martínez; Edgar Sánchez-Sinencio (IEEE J. Solid State Circuits, 2011)

A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing. - Xi Chen; Zhuizhuan Yu; Sebastian Hoyos; Brian M. Sadler; José Silva-Martínez (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Corrections to "A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing". - Xi Chen; Zhuizhuan Yu; Sebastian Hoyos; Brian M. Sadler; José Silva-Martínez (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Clock-Jitter-Tolerant Wideband Receivers: An Optimized Multichannel Filter-Bank Approach. - Sebastian Hoyos; Srikanth Pentakota; Zhuizhuan Yu; Ehab Sobhy Abdel Ghany; Xi Chen; Ramy Saad; Samuel Palermo; José Silva-Martínez (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Electrothermal Design Procedure to Observe RF Circuit Power and Linearity Characteristics With a Homodyne Differential Temperature Sensor. - Marvin Onabajo; Josep Altet; Eduardo Aldrete-Vidrio; Diego Mateo; José Silva-Martínez (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Low-power 3rd-order continuous-time low-pass sigma-delta analog-to-digital converter for wideband applications. - Kunmo Kim; José Silva-Martínez (MWSCAS, 2012)

Blocker and jitter tolerant wideband ΣΔ modulators. - José Silva-Martínez; Aydin Ilker Karsilayan; Hemasundar Mohan Geddada (MWSCAS, 2012)

A Sub-Nyquist Rate Compressive Sensing Data Acquisition Front-End. - Xi Chen; Ehab Ahmed Sobhy; Zhuizhuan Yu; Sebastian Hoyos; José Silva-Martínez; Samuel Palermo; Brian M. Sadler (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

A Self-Sustained CMOS Microwave Chemical Sensor Using a Frequency Synthesizer. - Ahmed A. Helmy; Hyung-Joon Jeon; Yung-Chung Lo; Andreas J. Larsson; Raghavendra Kulkarni; Jusung Kim; José Silva-Martínez; Kamran Entesari (IEEE J. Solid State Circuits, 2012)

An LC Quadrature VCO Using Capacitive Source Degeneration Coupling to Eliminate Bi-Modal Oscillation. - Haitao Tong; Shanfeng Cheng; Yung-Chung Lo; Aydin I. Karsilayan; José Silva-Martínez (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations. - Raghavendra Kulkarni; Jusung Kim; Hyung-Joon Jeon; Jianhong Xiao; José Silva-Martínez (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A current-mode flash ADC for low-power continuous-time sigma delta modulators. - Chang-Joon Park; Hemasundar Mohan Geddada; Aydin I. Karsilayan; José Silva-Martínez; Marvin Onabajo (ISCAS, 2013)

An external capacitor-less low drop-out regulator with superior PSR and fast transient response. - Saikrishna Ganta; Chang-Joon Park; Daniel Gitzel; Rafael Rivera; José Silva-Martínez (MWSCAS, 2013)

Robust compensation scheme for low power capacitor-less low dropout voltage regulator. - Daniel Gitzel; Rafael Rivera; José Silva-Martínez (MWSCAS, 2013)

Efficient calibration scheme for high-resolution pipelined ADCs. - Andreas Larsson; José Silva-Martínez (MWSCAS, 2013)

Envelope tracking technique with bang-bang slew-rate enhancer for linear wideband RF PAs. - Richard Turkson; Suraj Prakash; José Silva-Martínez; Herminio Martínez-Garcia (MWSCAS, 2013)

Low-Power, Low-Cost CMOS Direct-Conversion Receiver Front-End for Multistandard Applications. - Jusung Kim; José Silva-Martínez (IEEE J. Solid State Circuits, 2013)

A 1.5 ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links With Up to 40 Times Event-Rate Dependent Power Savings. - Carlos Zamarreño-Ramos; Raghavendra Kulkarni; José Silva-Martínez; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (IEEE Trans. Biomed. Circuits Syst., 2013)

Dual-Level Adaptive Supply Voltage System for Variation Resilience. - Kyu-Nam Shim; Jiang Hu; José Silva-Martínez (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy. - Hyung-Joon Jeon; Raghavendra Kulkarni; Yung-Chung Lo; Jusung Kim; José Silva-Martínez (IEEE J. Solid State Circuits, 2013)

A 44.9% PAE digitally-assisted linear power amplifier in 40 nm CMOS. - Haoyu Qian; José Silva-Martínez (A-SSCC, 2014)

Review of temperature sensors as monitors for RF-MMW built-in testing and self-calibration schemes. - Josep Altet; Eduardo Aldrete-Vidrio; Ferran Reverter; Didac Gómez; José Luis González 001; Marvin Onabajo; José Silva-Martínez; B. Martineau; X. Perpiñà; Louay Abdallah; Haralampos-G. D. Stratigopoulos; Xavier Aragonès; et al. (MWSCAS, 2014)

Design of minimally-invasive all-pole analog lowpass filters. - Saiteja Damera; Aydin Ilker Karsilayan; José Silva-Martínez (MWSCAS, 2014)

Blocker tolerant wideband continuous time sigma-delta modulator for wireless applications. - Hemasundar Mohan Geddada; Chang-Joon Park; José Silva-Martínez; Aydin Ilker Karsilayan (MWSCAS, 2014)

Design techniques for external capacitor-less LDOs with high PSR over wide frequency range. - Chang-Joon Park; José Silva-Martínez; Marvin Onabajo (MWSCAS, 2014)

Welcome to MWSCAS 2014. - José Silva-Martínez; Edgar Sánchez-Sinencio; José G. Delgado-Frias; Randall L. Geiger (MWSCAS, 2014)

External Capacitor-Less Low Drop-Out Regulator With 25 dB Superior Power Supply Rejection in the 0.4-4 MHz Range. - Chang-Joon Park; Marvin Onabajo; José Silva-Martínez (IEEE J. Solid State Circuits, 2014)

General Analysis of Feedback DAC's Clock Jitter in Continuous-Time Sigma-Delta Modulators. - Alexander Edward; José Silva-Martínez (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 0.6ps jitter 2-16 GHz 130nm CMOS frequency synthesizer for broadband applications. - Yung-Chung Lo; Negar Rashidi; Yin-Huan Hwang; José Silva-Martínez (ISCAS, 2015)

A 75 MHz BW 68dB DR CT-ΣΔ modulator with single amplifier biquad filter and a broadband low-power common-gate summing technique. - Carlos Briseno-Vidrios; Alexander Edward; Ayman Shafik; Samuel Palermo; José Silva-Martínez (VLSIC, 2015)

Design Techniques to Improve Blocker Tolerance of Continuous-Time ΔΣ ADCs. - Hemasundar Mohan Geddada; Chang-Joon Park; Hyung-Joon Jeon; José Silva-Martínez; Aydin Ilker Karsilayan; Douglas Garrity (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain. - Hyung-Joon Jeon; José Silva-Martínez; Sebastian Hoyos (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Efficient Broadband Current-Mode Adder- Quantizer Design for Continuous-Time Sigma-Delta Modulators. - Chang-Joon Park; Marvin Onabajo; Hemasundar Mohan Geddada; Aydin Ilker Karsilayan; José Silva-Martínez (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A digital-circuit-based evolutionary-computation algorithm for time-interleaved ADC background calibration. - Dadian Zhou; Claudio Talarico; José Silva-Martínez (SoCC, 2016)

A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer. - Carlos Briseno-Vidrios; Alexander Edward; Negar Rashidi; José Silva-Martínez (IEEE J. Solid State Circuits, 2016)

A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS. - Haoyu Qian; Qiyuan Liu 001; José Silva-Martínez; Sebastian Hoyos (IEEE J. Solid State Circuits, 2016)

A 13bit 200MS/S pipeline ADC with current-mode MDACs. - Carlos Briseno-Vidrios; Dadian Zhou; Suraj Prakash; Qiyuan Liu 001; Alexander Edward; José Silva-Martínez (ISCAS, 2017)

High-performance continuous-time MASH sigma-delta ADCs for broadband wireless applications. - Qiyuan Liu 001; Alexander Edward; Carlos Briseno-Vidrios; Negar Rashidi; José Silva-Martínez (MWSCAS, 2017)

A 200MSPS time-interleaved 12-bit ADC system with digital calibration. - Aditya Bommireddipalli; Dadian Zhou; Claudio Talarico; José Silva-Martínez; Aydin I. Karsilayan (MWSCAS, 2017)

Algorithmic-pipelined ADC with a modified residue curve for better linearity. - Mohammad H. Naderi; José Silva-Martínez (MWSCAS, 2017)

A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage. - Carlos Briseno-Vidrios; Alexander Edward; Ayman Shafik; Samuel Palermo; José Silva-Martínez (IEEE J. Solid State Circuits, 2017)

A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS. - Alexander Edward; Qiyuan Liu 001; Carlos Briseno-Vidrios; Martin Kinyua; Eric G. Soenen; Aydin Ilker Karsilayan; José Silva-Martínez (IEEE J. Solid State Circuits, 2017)

A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques. - Qiyuan Liu 001; Alexander Edward; Martin Kinyua; Eric G. Soenen; José Silva-Martínez (IEEE J. Solid State Circuits, 2017)

Low-Power Gm-C Filter Employing Current-Reuse Differential Difference Amplifiers. - John S. Mincey; Carlos Briseno-Vidrios; José Silva-Martínez; Christopher T. Rodenbeck (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Multitone ACLR and Its Applications to Linear PA Design. - Haoyu Qian; José Silva-Martínez (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Compressed Level Crossing Sampling for Ultra-Low Power IoT Devices. - Jun Zhou 002; Amir Tofighi Zavareh; Robin Gupta; Liang Liu 002; Zhongfeng Wang 001; Brian M. Sadler; José Silva-Martínez; Sebastian Hoyos (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Low noise RF quadrature VCO using tail-switch network-based coupling in 40 nm CMOS. - Venkatraman Natarajan; Mohammad H. Naderi; José Silva-Martínez (CICC, 2018)

A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs. - Carlos Briseno-Vidrios; Dadian Zhou; Suraj Prakash; Qiyuan Liu 001; Alexander Edward; Eric G. Soenen; Martin Kinyua; José Silva-Martínez (IEEE J. Solid State Circuits, 2018)

Operational Transconductance Amplifier With Class-B Slew-Rate Boosting for Fast High-Performance Switched-Capacitor Circuits. - Mohammad H. Naderi; Suraj Prakash; José Silva-Martínez (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS. - Qiyuan Liu 001; Alexander Edward; Dadian Zhou; José Silva-Martínez (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications. - John S. Mincey; Eric C. Su; José Silva-Martínez; Christopher T. Rodenbeck (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Efficient Broadband Class AB Amplifier. - José Silva-Martínez; Tanwei Yan; Junning Jiang; Jian Shao (MWSCAS, 2019)

When Less Is More ... Few Bit ADCs in RF Systems. - Christopher T. Rodenbeck; Matthew Martinez; Joshua B. Beun; José Silva-Martínez; Aydin Ilker Karsilayan; Robert Liechty (IEEE Access, 2019)

A 3-6-GHz Highly Linear I-Channel Receiver With Over +3.0-dBm In-Band P1dB and 200-MHz Baseband Bandwidth Suitable for 5G Wireless and Cognitive Radio Applications. - Junning Jiang; Jusung Kim; Aydin Ilker Karsilayan; José Silva-Martínez (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers. - Mohammad H. Naderi; Chulhyun Park; Suraj Prakash; Martin Kinyua; Eric G. Soenen; José Silva-Martínez (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration. - Dadian Zhou; Carlos Briseno-Vidrios; Junning Jiang; Chulhyun Park; Qiyuan Liu 001; Eric G. Soenen; Martin Kinyua; José Silva-Martínez (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 3 to 6 GHz Highly Linear I-Channel Receiver with over +3.0 dBm In-Band P1dB and 200 MHz Baseband Bandwidth Suitable for 5G Wireless and Cognitive Radio Applications. - Jusung Kim; Junning Jiang; José Silva-Martínez; Aydin Ilker Karsilayan (ISCAS, 2020)

A Blind Calibration Scheme for Switched-Capacitor Pipeline Analog-to-Digital Converters. - Juan A. Bozzo; Angel Abusleme; José Silva-Martínez (LASCAS, 2020)

A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator. - Dadian Zhou; Junning Jiang; Qiyuan Liu 001; Eric G. Soenen; Martin Kinyua; José Silva-Martínez (IEEE J. Solid State Circuits, 2020)

A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier. - Chulhyun Park; Tao Chen 006; Kyoohyun Noh; Dadian Zhou; Suraj Prakash; Mohammadhossein Naderi Alizadeh; Aydin I. Karsilayan; Degang Chen 001; Randall L. Geiger; José Silva-Martínez (IEEE Trans. Circuits Syst., 2020)

An Efficient Sinusoid-Like Pseudo Random Sequence Modulator/Demodulator System With Reduced Adjacent Channel Leakage and High Rejection to Random and Systematic Interference. - Jian Shao; Aydin Ilker Karsilayan; Christopher T. Rodenbeck; José Silva-Martínez (IEEE Trans. Circuits Syst., 2020)

MWSCAS Guest Editorial Special Issue Based on the 62nd International Midwest Symposium on Circuits and Systems. - José Silva-Martínez; José G. Delgado-Frias (IEEE Trans. Circuits Syst., 2020)

An Ultrafast Multibit/Stage Pipelined ADC Testing and Calibration Method. - Tao Chen 006; Chulhyun Park; Shravan K. Chaganti; José Silva-Martínez; Randall L. Geiger; Degang Chen 001 (IEEE Trans. Instrum. Meas., 2020)

A Low-Cost On-Chip Built-In Self-Test Solution for ADC Linearity Test. - Tao Chen 006; Chulhyun Park; Hao Meng; Dadian Zhou; José Silva-Martínez; Randall L. Geiger; Degang Chen 001 (IEEE Trans. Instrum. Meas., 2020)

Thermoelectric Energy Harvesting for Implantable Medical Devices. - Thomas Janes; Seth Petrosky; Troy Buhr; Aydin I. Karsilayan; Jose Silva-Martinez; David Genzer; Vighnesh Das; Larry J. Stotts (EMBC, 2021)

Recent Advances on Linear Low-Dropout Regulators. - José Silva-Martínez; Xiaosen Liu; Dadian Zhou (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Practical and Design oriented approach to teaching circuits. - Jose Silva-Martinez; Marvin Onabajo; Ayesha Mayhugh (ISCAS, 2022)

An Interference-Tolerant Synchronization Scheme for Wireless Communication Systems Based on Direct Sequence Spread Spectrum. - Jian Shao; Aydin Ilker Karsilayan; Christopher T. Rodenbeck; José Silva-Martínez (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

X-Band CMOS Rectifier With 4% Efficiency at -35 dBm for Wireless Power Transmission. - Troy Buhr; Aydin I. Karsilayan; Jose Silva-Martinez; Christopher T. Rodenbeck; Brian B. Tierney; Yanghyo Rod Kim (IEEE Access, 2023)

X-Band Phased-Array Transmitter Architecture with Power Transfer Optimization Algorithm for Space Solar Power System: A Case Study. - Mitchell Clark; Thomas Raguso; James Alexaner; Troy Buhr; Aydin Karsilayar; Jose Silva-Martinez (MWSCAS, 2024)

Look-Up Table-Based Digital Calibration for the Correction of Pipeline Analog-to-Digital Converter Non-Idealities. - Shangfeng Qiu; Dadian Zhou; Martin Kinyua; Jose Silva-Martinez (IEEE Access, 2024)

Matrix-Based Digital Calibration Technique for High-Performance SAR and Pipeline ADCs. - Amr Walid; Dadian Zhou; Jose Silva-Martinez (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Fractional Spur Cancellation Technique for Fractional-N Frequency Synthesizers Enabled by Dual Loop Phase Clamping. - Tanwei Yan; Junning Jiang; Jose Silva-Martinez (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)