A Boundary Scan Test Controller for Hierarchical BIST. - José M. M. Ferreira; Filipe S. Pinto; José Silva Matos (ITC, 1992)

Control and Observation of Analog Nodes in Mixed-Signal Boards. - José Silva Matos; Ana C. Leão; João Canas Ferreira (ITC, 1993)

An Approach to Testability Improvement of Mixed-Signal Boards. - José Silva Matos; João Canas Ferreira; Ana C. Leão; José Machado da Silva (ISCAS, 1994)

Architecture of test support ICs for mixed-signal testing. - José Silva Matos; João Canas Ferreira; Ana C. Leão; José Machado da Silva (VTS, 1994)

Evaluation of iDD/vOUT Cross-Correlation for Mixed Current/Voltage Testing of Analogue and Mixed-Signal Circuits. - José Machado da Silva; José Silva Matos (ED&TC, 1996)

ProHos-1 - A Vector Processor for the Efficient Estimation of Higher-Order Moments. - José Carlos Alves; André T. Puga; Luís Corte-Real; José Silva Matos (VECPAR, 1996)

Mixed current/voltage observation towards effective testing of analog and mixed-signal circuits. - José Machado da Silva; José Silva Matos; Ian M. Bell; Gaynor E. Taylor (J. Electron. Test., 1996)

A vector architecture for higher-order moments estimation. - José Carlos Alves; André T. Puga; Luís Corte-Real; José Silva Matos (ICASSP, 1997)

Implementation of Mixed Current/Voltage Testing Using the IEEE P1149.4 Infrastructure. - José Machado da Silva; Ana C. Leão; José Silva Matos; José Carlos Alves (ITC, 1997)

RVC - A Reconfigurable Coprocessor for Vector Processing Applications. - José Carlos Alves; José Silva Matos (FCCM, 1998)

A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware. - João Canas Ferreira; José Silva Matos (FCCM, 1998)

Flexible hardware acceleration for nesting problems. - João Canas Ferreira; José Carlos Alves; Célio Albuquerque 001; José Fernando Oliveira; José Soeiro Ferreira; José Silva Matos (ICECS, 1998)

Mixed hardware/software applications on dynamically reconfigurable hardware. - João Canas Ferreira; José Silva Matos (ICECS, 1998)

Mixed-Signal Board Level DfT Techniques Using IEEE P1149.4. - José Silva Matos; José Machado da Silva (ICECS, 1998)

Computer Organisation, Programming and Benchmarking - Introduction. - José Silva Matos (VECPAR, 1998)

FAFNER-Accelerating Nesting Problems with FPGAs. - José Carlos Alves; João Canas Ferreira; C. Albuquerque; José Fernando Oliveira; José Soeiro Ferreira; José Silva Matos (FCCM, 1999)

Mixed-Signal BIST Using Correlation and Reconfigurable Hardware. - José Machado da Silva; J. Soeiro Duarte; José Silva Matos (DATE, 2000)

ADC testing using joint time-frequency analysis. - Hélio Sousa Mendonça; José Machado da Silva; José Silva Matos (Comput. Stand. Interfaces, 2001)

A Development Support System for Applications That Use Dynamically Reconfigurable Hardware. - João Canas Ferreira; José Silva Matos (FPL, 2004)

A processor for testing mixed-signal cores in System-on-Chip. - Francisco Duarte; José Machado da Silva; José Carlos Alves; G. A. Pinho; José Silva Matos (DSD, 2005)

MICPRO DSD 2013 Special Issue. - José Silva Matos; Francesco Leporati (Microprocess. Microsystems, 2014)

MICPRO DSD 2014 special issue. - Francesco Leporati; José Silva Matos (Microprocess. Microsystems, 2015)

Scalable hardware architecture for disparity map computation and object location in real-time. - Pedro Miguel Salgueiro dos Santos; João Canas Ferreira; José Silva Matos (J. Real Time Image Process., 2016)