IC Defects-Based Testability Analysis. - José T. de Sousa; Fernando M. Gonçalves; João Paulo Teixeira 001 (ITC, 1991)

Physical design of testable CMOS digital integrated circuits. - José T. de Sousa; Fernando M. Gonçalves; João Paulo Teixeira 001 (IEEE J. Solid State Circuits, 1991)

Physical DFT for High Coverage of Realistic Faults. - M. Saraiva; P. Casimiro; Marcelino B. Santos; José T. de Sousa; Fernando M. Gonçalves; Isabel C. Teixeira; João Paulo Teixeira 001 (ITC, 1992)

Fault Modeling and Defect Level Projections in Digital ICs. - José T. de Sousa; Fernando M. Gonçalves; João Paulo Teixeira 001; Thomas W. Williams (EDAC-ETC-EUROASIC, 1994)

Realistic Fault Extraction for Boards. - José T. de Sousa; T. Shen; Peter Y. K. Cheung (ED&TC, 1996)

Defect level evaluation in an IC design environment. - José T. de Sousa; Fernando M. Gonçalves; João Paulo Teixeira 001; Cristoforo Marzocca; Francesco Corsi; Thomas W. Williams (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Improved diagnosis of realistic interconnect shorts. - José T. de Sousa; Peter Y. K. Cheung (ED&TC, 1997)

Diagnosis of Boards for Realistic Interconnect Shorts. - José T. de Sousa; Peter Y. K. Cheung (J. Electron. Test., 1997)

A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware. - Miron Abramovici; José T. de Sousa; Daniel G. Saab (DAC, 1999)

A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware. - Miron Abramovici; José T. de Sousa (FCCM, 1999)

On Defect-Level Estimation and the Clustering Effect. - José T. de Sousa (VLSI, 1999)

Reducing the Complexity of Defect Level Modeling Using the Clustering Effect. - José T. de Sousa; Vishwani D. Agrawal (DATE, 2000)

A SAT Solver Using Reconfigurable Hardware and Virtual Logic. - Miron Abramovici; José T. de Sousa (J. Autom. Reason., 2000)

A Configurable Hardware/Software Approach to SAT Solving. - José T. de Sousa; J. M. da Silva; Miron Abramovici (FCCM, 2001)

On Implementing a Configware/Software SAT Solver. - N. A. Reis; José T. de Sousa (FCCM, 2002)

DARP - A Digital Audio Reconfigurable Processor. - José T. de Sousa; Fernando M. Gonçalves; Nuno Barreiro; João Moura 002 (FPL, 2002)

Heuristic-Based Backtracking for Propositional Satisfiability. - Ateet Bhalla; Inês Lynce; José T. de Sousa; João Marques-Silva 001 (EPIA, 2003)

Fault Simulation Using Partially Reconfigurable Hardware. - Abilio Parreira; João Paulo Teixeira 001; A. Pantelimon; Marcelino B. Santos; José T. de Sousa (FPL, 2003)

Heuristic Backtracking Algorithms for SAT. - Ateet Bhalla; Inês Lynce; José T. de Sousa; João Marques-Silva 001 (MTV, 2003)

Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor. - Carlos J. Tavares; C. Bungardean; G. M. Matos; José T. de Sousa (FPL, 2004)

Guest Editors' Introduction: Field Programmable Logic and Applications. - Peter Y. K. Cheung; George A. Constantinides; José T. de Sousa (IEEE Trans. Computers, 2004)

A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits. - Victor Gonçalves; José T. de Sousa; Fernando M. Gonçalves (FPL, 2005)

Heuristic-Based Backtracking Relaxation for Propositional Satisfiability. - Ateet Bhalla; Inês Lynce; José T. de Sousa; João Marques-Silva 001 (J. Autom. Reason., 2005)

A fast SAT solver algorithm best suited to reconfigurable hardware. - Romanelli Lodron Zuim; José T. de Sousa; Claudionor José Nunes Coelho Jr. (SBCCI, 2006)

A Fast SAT Solver Strategy Based on Negated Clauses. - Romanelli Lodron Zuim; José T. de Sousa; Claudionor José Nunes Coelho Jr. (VLSI-SoC, 2006)

Decision heuristic for Davis Putnam, Loveland and Logemann algorithm satisfiability solving based on cube subtraction. - Romanelli Lodron Zuim; José T. de Sousa; Claudionor Coelho (IET Comput. Digit. Tech., 2008)

An ultra-low power low-IF GFSK demodulator for Bluetooth-LE applications. - Marco Silva Pereira; João Caldinhas Vaz; Carlos Azeredo Leme; José T. de Sousa; João Costa Freire (ISCAS, 2015)

Versat, a Minimal Coarse-Grain Reconfigurable Array. - João D. Lopes; José T. de Sousa (VECPAR, 2016)

K-means clustering on CGRA. - João D. Lopes; José T. de Sousa; Horácio C. Neto; Mário P. Véstias (FPL, 2017)

Parallel dot-products for deep learning on FPGA. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (FPL, 2017)

Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (FPL, 2018)

Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (FPL, 2019)

Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores. - Luís Fiolhais; Fernando M. Gonçalves; Rui Policarpo Duarte; Mário P. Véstias; José T. de Sousa (ISCAS, 2019)

Implementing CNNs Using a Linear Array of Full Mesh CGRAs. - Valter Mário; João D. Lopes; Mário P. Véstias; José T. de Sousa (ARC, 2020)

A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (IEEE Access, 2020)

Moving Deep Learning to the Edge. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (Algorithms, 2020)

A fast and scalable architecture to run convolutional neural networks in low density FPGAs. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (Microprocess. Microsystems, 2020)

A Full Featured Configurable Accelerator for Object Detection With YOLO. - Daniel Pestana; Pedro R. Miranda; João D. Lopes; Rui Policarpo Duarte; Mário P. Véstias; Horácio C. Neto; José T. de Sousa (IEEE Access, 2021)

IOb-Cache: A High-Performance Configurable Open-Source Cache. - João V. Roque; João D. Lopes; Mário P. Véstias; José T. de Sousa (Algorithms, 2021)

Configurable Hardware Core for IoT Object Detection. - Pedro R. Miranda; Daniel Pestana; João D. Lopes; Rui Policarpo Duarte; Mário P. Véstias; Horácio C. Neto; José T. de Sousa (Future Internet, 2021)

Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA. - David Mota; Helena Cruz; Pedro R. Miranda; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto; Mário P. Véstias (IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2022)

Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (ACM Trans. Reconfigurable Technol. Syst., 2023)

PT-Float: A Floating-Point Unit with Dynamically Varying Exponent and Fraction Sizes. - José T. de Sousa; João D. Lopes; Micaela Serôdio; Horácio C. Neto; Mário P. Véstias (ARITH, 2024)

Coarse-Grained Reconfigurable Arrays for High-Performance Low-Power Deep Neural Networks on Embedded Devices. - João D. Lopes; Horácio C. Neto; José T. de Sousa (DoCEIS, 2025)