Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. - Josef Strnadel; Zdenek Kotásek (DSD, 2002)

Test scheduling for embedded systems. - Zdenek Kotásek; Daniel Mika; Josef Strnadel (DSD, 2003)

The Identification of registers in RTL Structures for the Test Application. - Daniel Mika; Josef Strnadel; Zdenek Kotásek (ISoLA (Preliminary proceedings), 2004)

Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies. - Josef Strnadel; Zdenek Kotásek (DSD, 2005)

Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. - Tomas Pecenka; Zdenek Kotásek; Lukás Sekanina; Josef Strnadel (Evolvable Hardware, 2005)

Power-Constrained, Sessionless SoC Test Scheduling Based on Exploration of I-Schedule State-Space. - Josef Strnadel (DDECS, 2006)

Testability Estimation Based on Controllability and Observability Parameters. - Tomas Pecenka; Josef Strnadel; Zdenek Kotásek; Lukás Sekanina (DSD, 2006)

Novel Optimizing Approach in the Area of STEP-Based Construction of Sessionless, Power-Constrainted, TAM and Time Optimal Test Schedules. - Josef Strnadel; Arghya Kumar Dhali (ECBS, 2006)

SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. - Josef Strnadel; Zdenek Kotásek (ECBS, 2006)

Testability Analysis and Improvements of Register-Transfer Level Digital Circuits. - Josef Strnadel (Comput. Artif. Intell., 2006)

Test Controller Synthesis Constrained by Circuit Testability Analysis. - Richard Ruzicka; Josef Strnadel (DSD, 2007)

TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path. - Josef Strnadel (DSD, 2008)

Measuring CADeT Performance by Means of FITTest_BENCH06 Benchmark Circuits. - Josef Strnadel; Tomas Pecenka; Zdenek Kotásek (Comput. Informatics, 2008)

Reduction of power dissipation through parallel optimization of test vector and scan register sequences. - Zdenek Kotásek; Jaroslav Skarvada; Josef Strnadel (DDECS, 2010)

The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. - Zdenek Kotásek; Jaroslav Skarvada; Josef Strnadel (DSD, 2010)

The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. - Jaroslav Skarvada; Zdenek Kotásek; Josef Strnadel (ICES, 2010)

On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits. - Michal Rumplík; Josef Strnadel (DSD, 2011)

Monitoring-driven HW/SW interrupt overload prevention for embedded real-time systems. - Josef Strnadel (DDECS, 2012)

On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels. - Josef Strnadel; Frantisek Slimarik (DSD, 2012)

Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates. - Josef Strnadel (ARCS, 2013)

On design of priority-driven load-adaptive monitoring-based hardware for managing interrupts in embedded event-triggered real-time systems. - Josef Strnadel (DDECS, 2013)

Comparing Availability-Aware Real-Time Schedulers by Means of Configurable Experimental Framework. - Josef Strnadel; Martin Pokorny (DSD, 2014)

Impact of Software Fault Tolerance to Fault Effects in OS-Driven RT Systems. - Josef Strnadel; Frantisek Slimarik (Comput. Informatics, 2014)

Comparison of Generally Applicable Mechanisms for Preventing Embedded Event-Driven Real-Time Systems from Interrupt Overloads. - Josef Strnadel (ECBS-EERC, 2015)

On Creation and Analysis of Reliability Models by Means of Stochastic Timed Automata and Statistical Model Checking: Principle. - Josef Strnadel (ISoLA (1), 2016)

On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model Checking. - Josef Strnadel (DSD, 2017)

Statistical Model Checking of Processor Systems in Various Interrupt Scenarios. - Josef Strnadel (ISoLA (2), 2018)

Predictability Analysis of Interruptible Systems by Statistical Model Checking. - Josef Strnadel (IEEE Des. Test, 2018)

Using Statistical Model Checking to Assess Reliability for Bathtub-Shaped Failure Rates. - Josef Strnadel (DATE, 2019)

Statistical Model Checking of Approximate Circuits: Challenges and Opportunities. - Josef Strnadel (DATE, 2020)

Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults. - Josef Strnadel (DDECS, 2021)

Analyzing Dynamic Aspects of AxC Systems by Means of Statistical Model Checking. - Josef Strnadel (DDECS, 2022)

The LoLiPoP-IoT Project: Long Life Power Platforms for Internet of Things. - Jakub Lojda; Josef Strnadel; Václav Simek; Pavel Smrz; Mike Hayes; Ralf Popp (DSD, 2024)

First Steps Towards Unified Low-Power IoT Design: The "DYNAMIC" Framework. - Jakub Lojda; Josef Strnadel; Pavel Smrz; Václav Simek (EWDTS, 2024)

On SMC-Based Dependability Analysis in LoLiPoP-IoT Project. - Josef Strnadel; Jakub Lojda; Pavel Smrz; Václav Simek (AISoLA, 2024)

Multi-Partner Project: LoLiPoP-IoT - Design and Simulation of Energy-Efficient Devices for the Internet of Things. - Jakub Lojda; Josef Strnadel; Pavel Smrz; Václav Simek (DATE, 2025)