Using Sacks to Organize Registers in VLIW Machines. - Josep Llosa; Mateo Valero; José A. B. Fortes; Eduard Ayguadé (CONPAR, 1994)

Non-Consistent Dual Register Files to Reduce Register Pressure. - Josep Llosa; Mateo Valero; Eduard Ayguadé (HPCA, 1995)

Hypernode reduction modulo scheduling. - Josep Llosa; Mateo Valero; Eduard Ayguadé; Antonio González 001 (MICRO, 1995)

Swing module scheduling: a lifetime-sensitive approach. - Josep Llosa; Antonio González 001; Eduard Ayguadé; Mateo Valero (IEEE PACT, 1996)

Heuristics for Register-Constrained Software Pipelining. - Josep Llosa; Mateo Valero; Eduard Ayguadé (MICRO, 1996)

Allocating Lifetimes to Queues in Software Pipelined Architectures. - Marcio Merino Fernandes; Josep Llosa; Nigel P. Topham (Euro-Par, 1997)

Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs. - David López 001; Mateo Valero; Josep Llosa; Eduard Ayguadé (International Conference on Supercomputing, 1997)

Resource Widening Versus Replication: Limits and Performance-cost Trade-off. - David López 001; Josep Llosa; Mateo Valero; Eduard Ayguadé (International Conference on Supercomputing, 1998)

Partitioned Schedules for Clustered VLIW Architectures. - Marcio Merino Fernandes; Josep Llosa; Nigel P. Topham (IPPS/SPDP, 1998)

Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures. - David López 001; Josep Llosa; Mateo Valero; Eduard Ayguadé (MICRO, 1998)

Quantitative Evaluation of Register Pressure on Software Pipelined Loops. - Josep Llosa; Eduard Ayguadé; Mateo Valero (Int. J. Parallel Program., 1998)

Modulo Scheduling with Reduced Register Pressure. - Josep Llosa; Mateo Valero; Eduard Ayguadé; Antonio González 001 (IEEE Trans. Computers, 1998)

Distributed Modulo Scheduling. - Marcio Merino Fernandes; Josep Llosa; Nigel P. Topham (HPCA, 1999)

Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures. - David López 001; Josep Llosa; Eduard Ayguadé; Mateo Valero (ICPP, 1999)

A Fast and Accurate Approach to Analyze Cache Memory Behavior (Research Note). - Xavier Vera; Josep Llosa; Antonio González 001; Nerina Bermudo (Euro-Par, 2000)

An efficient solver for Cache Miss Equations. - Nerina Bermudo; Xavier Vera; Antonio González 001; Josep Llosa (ISPASS, 2000)

Two-level hierarchical register file organization for VLIW processors. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (MICRO, 2000)

Improved spill code generation for software pipelined loops. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (PLDI, 2000)

Optimizing cache miss equations polyhedra. - Nerina Bermudo; Xavier Vera; Antonio González 001; Josep Llosa (SIGARCH Comput. Archit. News, 2000)

MIRS: Modulo Scheduling with Integrated Register Spilling. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (LCPC, 2001)

Modulo scheduling with integrated register spilling for clustered VLIW architectures. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (MICRO, 2001)

Lifetime-Sensitive Modulo Scheduling in a Production Environment. - Josep Llosa; Eduard Ayguadé; Antonio González 001; Mateo Valero; Jason Eckhardt (IEEE Trans. Computers, 2001)

Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures. - David López 001; Josep Llosa; Mateo Valero; Eduard Ayguadé (IEEE Trans. Computers, 2001)

Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms. - Jaume Abella 001; Antonio González 001; Josep Llosa; Xavier Vera (ICPP Workshops, 2002)

A comparative study of modulo scheduling techniques. - Josep M. Codina; Josep Llosa; Antonio González 001 (ICS, 2002)

Near-Optimal Padding for Removing Conflict Misses. - Xavier Vera; Josep Llosa; Antonio González 001 (LCPC, 2002)

Reduced code size modulo scheduling in the absence of hardware support. - Josep Llosa; Stefan M. Freudenberger (MICRO, 2002)

Optimizing Program Locality Through CMEs and GAs. - Xavier Vera; Jaume Abella 001; Antonio González 001; Josep Llosa (IEEE PACT, 2003)

Hierarchical Clustered Register File Organization for VLIW Processors. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (IPDPS, 2003)

Kilo-instruction Processors. - Adrián Cristal; Daniel Ortega; Josep Llosa; Mateo Valero (ISHPC, 2003)

Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. - Miquel Pericàs; Eduard Ayguadé; Javier Zalamea; Josep Llosa; Mateo Valero (ISHPC, 2003)

A Case for Resource-conscious Out-of-order Processors. - Adrián Cristal; José F. Martínez; Josep Llosa; Mateo Valero (IEEE Comput. Archit. Lett., 2003)

Out-of-Order Commit Processors. - Adrián Cristal; Daniel Ortega; Josep Llosa; Mateo Valero (HPCA, 2004)

Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units. - Miquel Pericàs; Eduard Ayguadé; Javier Zalamea; Josep Llosa; Mateo Valero (SAMOS, 2004)

Future ILP processors. - Adrián Cristal; Josep Llosa; Mateo Valero; Daniel Ortega (Int. J. High Perform. Comput. Netw., 2004)

High-performance and low-power VLIW cores for numerical computations. - Miquel Pericàs; Eduard Ayguadé; Javier Zalamea; Josep Llosa; Mateo Valero (Int. J. High Perform. Comput. Netw., 2004)

Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (Int. J. Parallel Program., 2004)

A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. - Adrián Cristal; José F. Martínez; Josep Llosa; Mateo Valero (SIGARCH Comput. Archit. News, 2004)

A fast and accurate framework to analyze and optimize cache memory behavior. - Xavier Vera; Nerina Bermudo; Josep Llosa; Antonio González 001 (ACM Trans. Program. Lang. Syst., 2004)

Register Constrained Modulo Scheduling. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (IEEE Trans. Parallel Distributed Syst., 2004)

An accurate cost model for guiding data locality transformations. - Xavier Vera; Jaume Abella 001; Josep Llosa; Antonio González 001 (ACM Trans. Program. Lang. Syst., 2005)

Merge Logic for Clustered Multithreaded VLIW Processors. - Manoj Gupta 001; Fermín Sánchez; Josep Llosa (DSD, 2007)

Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration. - Kolin Paul; Joël Porquet; Josep Llosa (DSD, 2007)

Cluster-level simultaneous multithreading for VLIW processors. - Manoj Gupta 001; Fermín Sánchez; Josep Llosa (ICCD, 2007)

Power-efficient VLIW design using clustering and widening. - Miquel Pericàs; Eduard Ayguadé; Javier Zalamea; Josep Llosa; Mateo Valero (Int. J. Embed. Syst., 2008)

Hybrid multithreading for VLIW processors. - Manoj Gupta 001; Fermín Sánchez; Josep Llosa (CASES, 2009)

Thread Merging Schemes for Multithreaded Clustered VLIW Processors. - Manoj Gupta 001; Fermín Sánchez; Josep Llosa (ICPP, 2009)

A low cost split-issue technique to improve performance of SMT clustered VLIW processors. - Manoj Gupta 001; Fermín Sánchez; Josep Llosa (IPDPS, 2010)

CSMT: Simultaneous Multithreading for Clustered VLIW Processors. - Manoj Gupta 001; Fermín Sánchez; Josep Llosa (IEEE Trans. Computers, 2010)

Lightning Talks of EduHPC 2022. - Apan Qasem; Hartwig Anzt; Eduard Ayguadé; Katharine J. Cahill; Ramon Canal; Jany Chan; Eric Fosler-Lussier; Fritz Göbel; Arpan Jain; Marcel Koch; Mateusz Kuzak; Josep Llosa; et al. (EduHPC@SC, 2022)

ECCPA: Calculation of classical and quantum cross sections for elastic collisions of charged particles with atoms. - Francesc Salvat; Josep Llosa; Antonio M. Lallena; Julio Almansa (Comput. Phys. Commun., 2022)

The European master for HPC curriculum. - Pascal Bouvry; Mats Brorsson; Ramon Canal; Aryan Eftekhari; Siegfried Höfinger; Didier Smets; Harald Köstler; Tomás Kozubek; Ezhilmathi Krishnasamy; Josep Llosa; Alexandra Lukas-Rother; Xavier Martorell; et al. (J. Parallel Distributed Comput., 2025)