A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors. - Josep M. Codina; F. Jesús Sánchez; Antonio González 001 (IEEE PACT, 2001)

Graph-partitioning based instruction scheduling for clustered processors. - Alex Aletà; Josep M. Codina; F. Jesús Sánchez; Antonio González 001 (MICRO, 2001)

Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning. - Alex Aletà; Josep M. Codina; F. Jesús Sánchez; Antonio González 001; David R. Kaeli (IEEE PACT, 2002)

A comparative study of modulo scheduling techniques. - Josep M. Codina; Josep Llosa; Antonio González 001 (ICS, 2002)

Instruction Replication for Clustered Microarchitectures. - Alex Aletà; Josep M. Codina; Antonio González 001; David R. Kaeli (MICRO, 2003)

Removing communications in clustered microarchitectures through instruction replication. - Alex Aletà; Josep M. Codina; Antonio González 001; David R. Kaeli (ACM Trans. Archit. Code Optim., 2004)

Demystifying on-the-fly spill code. - Alex Aletà; Josep M. Codina; Antonio González 001; David R. Kaeli (PLDI, 2005)

Heterogeneous Clustered VLIW Microarchitectures. - Alex Aletà; Josep M. Codina; Antonio González 001; David R. Kaeli (CGO, 2007)

Virtual Cluster Scheduling Through the Scheduling Graph. - Josep M. Codina; F. Jesús Sánchez; Antonio González 001 (CGO, 2007)

A software-hardware hybrid steering mechanism for clustered microarchitectures. - Qiong Cai; Josep M. Codina; José González 002; Antonio González 001 (IPDPS, 2008)

Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading. - Carlos Madriles; Pedro López 001; Josep M. Codina; Enric Gibert; Fernando Latorre; Alejandro Martínez; Raúl Martínez; Antonio González 001 (PACT, 2009)

Boosting single-thread performance in multi-core systems through fine-grain multi-threading. - Carlos Madriles; Pedro López 001; Josep M. Codina; Enric Gibert; Fernando Latorre; Alejandro Martínez; Raúl Martínez; Antonio González 001 (ISCA, 2009)

AGAMOS: A Graph-Based Approach to Modulo Scheduling for Clustered Microarchitectures. - Alex Aletà; Josep M. Codina; F. Jesús Sánchez; Antonio González 001; David R. Kaeli (IEEE Trans. Computers, 2009)

A Co-designed HW/SW Approach to General Purpose Program Acceleration Using a Programmable Functional Unit. - Abhishek Deb; Josep M. Codina; Antonio González 001 (Interaction between Compilers and Computer Architectures, 2011)

SoftHV: a HW/SW co-designed processor with horizontal and vertical fusion. - Abhishek Deb; Josep M. Codina; Antonio González 001 (Conf. Computing Frontiers, 2011)

A Power-Efficient Co-designed Out-of-Order Processor. - Abhishek Deb; Josep M. Codina; Antonio González 001 (SBAC-PAD, 2011)

A HW/SW Co-designed Programmable Functional Unit. - Abhishek Deb; Josep M. Codina; Antonio González 001 (IEEE Comput. Archit. Lett., 2012)

Profiling Support for Runtime Managed Code: Next Generation Performance Monitoring Units. - Enric Gibert; Raúl Martínez; Carlos Madriles; Josep M. Codina (IEEE Comput. Archit. Lett., 2015)